mirror of https://github.com/thesofproject/sof.git
platform: mtk: add mt8186 memory layout and register definitions
Add memory layout and register address for mtk mt8186 Cache I-Cache: 64KB, 4-way Associativity D-Cache: 128KB, 4-way Associativity External Memory DRAM: DSP can access DRAM shared with CPU L2TCM: 512KB DSP SRAM POOL Currently, use phy addr:0x60000000, size:0x1000000 dma phy addr: 0x61000000, size: 0x0100000 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
This commit is contained in:
Tinghan Shen
Liam Girdwood
parent
c6ea9b9c20
commit
24e1b7f6ca
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2022 Mediatek. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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#ifndef MT_REG_BASE_H
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#define MT_REG_BASE_H
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#define MTK_REG_TOPCKGEN_BASE 0x10000000
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#define MTK_REG_TOPCKGEN_SIZE 0x1000
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#define MTK_REG_APMIXDSYS_BASE 0x1000C000
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#define MTK_REG_APMIXDSYS_SIZE 0x1000
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#define MTK_DSP_REG_BASE 0x10680000 /* DSP Register base */
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#define MTK_DSP_CFGREG_BASE 0x10680000
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#define MTK_DSP_CFGREG_SIZE 0x1000
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#define MTK_DSP_CKCTRL_BASE 0x10681000
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#define MTK_DSP_CKCTRL_SIZE 0x1000
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#define MTK_DSP_OS_TIMER_BASE 0x10683000
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#define MTK_DSP_OS_TIMER_SIZE 0x1000
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#define MTK_DSP_UART0_BASE 0x10684000
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#define MTK_DSP_UART0_SIZE 0x1000
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#define MTK_DSP_TIMER_BASE 0x1068E000
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#define MTK_DSP_TIMER_SIZE 0x1000
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#define MTK_DSP_BUS_BASE 0x1068F000
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#define MTK_DSP_BUS_SIZE 0x1000
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#define MTK_DSP_AFE_BASE 0x11210000
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#define MTK_DSP_AFE_SIZE 0xF000 /* register 8k, compacted sram 52k */
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#define MTK_ADSP_CFGREG_SW_RSTN (MTK_DSP_REG_BASE + 0x0000)
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#define MTK_ADSP_HIFI_IO_CONFIG (MTK_DSP_REG_BASE + 0x000c)
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#define MTK_ADSP_IRQ_STATUS (MTK_DSP_REG_BASE + 0x0010)
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#define MTK_ADSP_SW_INT_SET (MTK_DSP_REG_BASE + 0x0018)
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#define MTK_ADSP_SW_INT_CLR (MTK_DSP_REG_BASE + 0x001c)
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#define MTK_ADSP_SW_INT_32A (MTK_DSP_REG_BASE + 0x0020)
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#define MTK_ADSP_IRQ_MASK (MTK_DSP_REG_BASE + 0x0030)
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#define MTK_ADSP_GENERAL_IRQ_SET (MTK_DSP_REG_BASE + 0x0034)
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#define MTK_ADSP_GENERAL_IRQ_CLR (MTK_DSP_REG_BASE + 0x0038)
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#define MTK_ADSP_DVFSRC_STATE (MTK_DSP_REG_BASE + 0x003c)
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#define MTK_ADSP_DVFSRC_REQ (MTK_DSP_REG_BASE + 0x0040)
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#define MTK_ADSP_DDREN_REQ_0 (MTK_DSP_REG_BASE + 0x0044)
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#define MTK_ADSP_SPM_ACK (MTK_DSP_REG_BASE + 0x004c)
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#define MTK_ADSP_IRQ_EN (MTK_DSP_REG_BASE + 0x0050)
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#define MTK_ADSP_IRQ_POL_FIX (MTK_DSP_REG_BASE + 0x0054)
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#define MTK_ADSP_SPM_WAKEUPSRC_CORE0 (MTK_DSP_REG_BASE + 0x005c)
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#define MTK_ADSP_SEMAPHORE (MTK_DSP_REG_BASE + 0x0064)
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#define MTK_ADSP_DBG_SEL (MTK_DSP_REG_BASE + 0x0074)
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#define MTK_ADSP_DBG_INFO (MTK_DSP_REG_BASE + 0x0078)
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#define MTK_ADSP_WDT_CON_C0 (MTK_DSP_REG_BASE + 0x007c)
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#define MTK_ADSP_WDT_INIT_VALUE_C0 (MTK_DSP_REG_BASE + 0x0080)
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#define MTK_ADSP_WDT_CNT_C0 (MTK_DSP_REG_BASE + 0x0084)
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#define MTK_ADSP_WAKEUPSRC_MASK_C0 (MTK_DSP_REG_BASE + 0x00a0)
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#define MTK_ADSP_WAKEUPSRC_IRQ_C0 (MTK_DSP_REG_BASE + 0x00a4)
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#define MTK_ADSP2SPM_MBOX (MTK_DSP_REG_BASE + 0x00bc)
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#define MTK_SPM2ADSP_MBOX (MTK_DSP_REG_BASE + 0x00c0)
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#define MTK_GPR_RW_REG0 (MTK_DSP_REG_BASE + 0x0440)
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#define MTK_GPR_RW_REG1 (MTK_DSP_REG_BASE + 0x0444)
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#define MTK_GPR_RW_REG2 (MTK_DSP_REG_BASE + 0x0448)
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#define MTK_GPR_RW_REG3 (MTK_DSP_REG_BASE + 0x044c)
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#define MTK_GPR_RW_REG4 (MTK_DSP_REG_BASE + 0x0450)
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#define MTK_GPR_RW_REG5 (MTK_DSP_REG_BASE + 0x0454)
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#define MTK_GPR_RW_REG6 (MTK_DSP_REG_BASE + 0x0458)
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#define MTK_GPR_RW_REG7 (MTK_DSP_REG_BASE + 0x045c)
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#define MTK_GPR_RW_REG8 (MTK_DSP_REG_BASE + 0x0460)
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#define MTK_GPR_RW_REG9 (MTK_DSP_REG_BASE + 0x0464)
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#define MTK_GPR_RW_REG10 (MTK_DSP_REG_BASE + 0x0468)
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#define MTK_GPR_RW_REG11 (MTK_DSP_REG_BASE + 0x046c)
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#define MTK_GPR_RW_REG12 (MTK_DSP_REG_BASE + 0x0470)
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#define MTK_GPR_RW_REG13 (MTK_DSP_REG_BASE + 0x0474)
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#define MTK_GPR_RW_REG14 (MTK_DSP_REG_BASE + 0x0478)
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#define MTK_GPR_RW_REG15 (MTK_DSP_REG_BASE + 0x047c)
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#define MTK_GPR_RW_REG16 (MTK_DSP_REG_BASE + 0x0480)
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#define MTK_GPR_RW_REG17 (MTK_DSP_REG_BASE + 0x0484)
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#define MTK_GPR_RW_REG18 (MTK_DSP_REG_BASE + 0x0488)
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#define MTK_GPR_RW_REG19 (MTK_DSP_REG_BASE + 0x048c)
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#define MTK_GPR_RW_REG20 (MTK_DSP_REG_BASE + 0x0490)
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#define MTK_GPR_RW_REG21 (MTK_DSP_REG_BASE + 0x0494)
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#define MTK_GPR_RW_REG22 (MTK_DSP_REG_BASE + 0x0498)
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#define MTK_GPR_RW_REG23 (MTK_DSP_REG_BASE + 0x049c)
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#define MTK_GPR_RW_REG24 (MTK_DSP_REG_BASE + 0x04a0)
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#define MTK_GPR_RW_REG25 (MTK_DSP_REG_BASE + 0x04a4)
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#define MTK_GPR_RW_REG26 (MTK_DSP_REG_BASE + 0x04a8)
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#define MTK_GPR_RW_REG27 (MTK_DSP_REG_BASE + 0x04ac)
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#define MTK_GPR_RW_REG28 (MTK_DSP_REG_BASE + 0x04b0) /* use for tickless status */
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#define MTK_GPR_RW_REG29 (MTK_DSP_REG_BASE + 0x04b4)
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#define MTK_ADSP_CLK_BUS_UPDATE (MTK_DSP_REG_BASE + 0x04c0)
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#define MTK_ADSP_IRQ_OUT_MASK (MTK_DSP_REG_BASE + 0x0500)
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#define MTK_MBOX_IRQ_IN (MTK_DSP_REG_BASE + 0xB070)
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#define MTK_ADSP_BUS_SRC (MTK_DSP_BUS_BASE + 0x140)
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#define MTK_ADSPPLL_CON0 (MTK_REG_APMIXDSYS_BASE + 0x304)
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#define MTK_ADSPPLL_CON1 (MTK_REG_APMIXDSYS_BASE + 0x308)
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#define MTK_ADSPPLL_CON2 (MTK_REG_APMIXDSYS_BASE + 0x30C)
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#define MTK_ADSPPLL_CON3 (MTK_REG_APMIXDSYS_BASE + 0x310)
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#define MTK_CLK_MODE (MTK_REG_TOPCKGEN_BASE + 0x0)
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#define MTK_CLK_CFG_UPDATE (MTK_REG_TOPCKGEN_BASE + 0x8)
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#define MTK_CLK_CFG_11 (MTK_REG_TOPCKGEN_BASE + 0x0EC)
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#define MTK_CLK_CFG_11_SET (MTK_REG_TOPCKGEN_BASE + 0x0F0)
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#define MTK_CLK_CFG_11_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4)
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#define MTK_CLK_CFG_15 (MTK_REG_TOPCKGEN_BASE + 0x180)
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#define MTK_CLK_CFG_15_SET (MTK_REG_TOPCKGEN_BASE + 0x184)
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#define MTK_CLK_CFG_15_CLR (MTK_REG_TOPCKGEN_BASE + 0x188)
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/* MBOX registers */
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#define MTK_ADSP_MBOX_REG_BASE(x) (0x10686000 + (0x1000 * (x)))
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#define MTK_ADSP_MBOX_REG_SIZE (0x5000)
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#define MTK_ADSP_MBOX_IN_CMD(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x100)
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#define MTK_ADSP_MBOX_IN_CMD_CLR(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x108)
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#define MTK_ADSP_MBOX_OUT_CMD(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x104)
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#define MTK_ADSP_MBOX_OUT_CMD_CLR(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x10c)
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#endif /* MT_REG_BASE_H */
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@ -0,0 +1,220 @@
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// SPDX-License-Identifier: BSD-3-Clause
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//
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// Copyright(c) 2022 Mediatek. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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#ifdef __SOF_LIB_MEMORY_H__
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#ifndef __PLATFORM_LIB_MEMORY_H__
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#define __PLATFORM_LIB_MEMORY_H__
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#include <sof/lib/cache.h>
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/* data cache line alignment */
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#define PLATFORM_DCACHE_ALIGN sizeof(void *)
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/* physical DSP addresses */
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#define SRAM_BASE 0x4e100000
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#define SRAM_SIZE 0x100000
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/* reset vector + rodata + module_init + text + data + bss */
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#define SOF_DATA_SIZE 0x80000
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#define VECTOR_SIZE 0x700
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#define SRAM_START (SRAM_BASE + VECTOR_SIZE)
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#define DRAM_BASE 0x60000000
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#define DRAM0_SIZE 0x500000
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#define MAILBOX_BASE (DRAM_BASE + DRAM0_SIZE)
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#define DSP_SYS_SIZE 0xA00000
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#define UUID_ENTRY_ELF_BASE (SRAM_BASE + SOF_DATA_SIZE)
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#define UUID_ENTRY_ELF_SIZE 0x6000
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#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE)
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#define LOG_ENTRY_ELF_SIZE 0x20000
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#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
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#define EXT_MANIFEST_ELF_SIZE (SRAM_BASE + SRAM_SIZE - EXT_MANIFEST_ELF_BASE)
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/*
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* The Memory Layout on MT8186 are organised like this :-
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*
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* +--------------------------------------------------------------------------+
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* | Offset | Region | Size |
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* +---------------------+----------------+-----------------------------------+
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* | SRAM_START | RO Data | SOF_DATA_SIZE |
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* | | text | |
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* | | Data | |
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* | | BSS | |
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* +---------------------+----------------+-----------------------------------+
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* | fw_ready |
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* +---------------------+----------------+-----------------------------------+
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* | static_uuid |
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* +---------------------+----------------+-----------------------------------+
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* | static_log |
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* +---------------------+----------------+-----------------------------------+
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* | fw_metadata |
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* +---------------------+----------------+-----------------------------------+
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*
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_BASE | | |
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* +---------------------+----------------+-----------------------------------+
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*/
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/* Mailbox configuration */
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#define SRAM_OUTBOX_BASE MAILBOX_BASE
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#define SRAM_OUTBOX_SIZE 0x1000
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#define SRAM_OUTBOX_OFFSET 0
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#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
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#define SRAM_INBOX_SIZE 0x1000
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#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
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#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
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#define SRAM_DEBUG_SIZE 0x800
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#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
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#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
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#define SRAM_EXCEPT_SIZE 0x800
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#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
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#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
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#define SRAM_STREAM_SIZE 0x1000
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#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
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#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
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#define SRAM_TRACE_SIZE 0x1000
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#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
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/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/
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#define SOF_MAILBOX_SIZE \
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(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + \
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SRAM_EXCEPT_SIZE + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
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/* Heap section sizes for module pool */
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#define HEAP_RT_COUNT8 0
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#define HEAP_RT_COUNT16 48
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#define HEAP_RT_COUNT32 48
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#define HEAP_RT_COUNT64 32
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#define HEAP_RT_COUNT128 32
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#define HEAP_RT_COUNT256 32
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#define HEAP_RT_COUNT512 4
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#define HEAP_RT_COUNT1024 4
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#define HEAP_RT_COUNT2048 2
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#define HEAP_RT_COUNT4096 2
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/* Heap section sizes for system runtime heap */
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#define HEAP_SYS_RT_COUNT64 128
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#define HEAP_SYS_RT_COUNT512 16
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#define HEAP_SYS_RT_COUNT1024 8
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/* Heap configuration */
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#define HEAP_SYSTEM_BASE DRAM_BASE
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#define HEAP_SYSTEM_SIZE 0x6000
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#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE)
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/*24KB*/
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#define HEAP_SYS_RUNTIME_SIZE \
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(HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \
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HEAP_SYS_RT_COUNT1024 * 1024)
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#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE)
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/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/
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#define HEAP_RUNTIME_SIZE \
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(HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \
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HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \
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HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \
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HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 + \
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HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096)
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#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE)
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#define HEAP_BUFFER_SIZE \
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(DRAM0_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE - \
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HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE)
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#define HEAP_BUFFER_BLOCK_SIZE 0x100
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#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE)
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#define PLATFORM_HEAP_SYSTEM 1 /* one per core */
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#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */
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#define PLATFORM_HEAP_RUNTIME 1
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#define PLATFORM_HEAP_BUFFER 1
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/* Stack configuration */
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#define SOF_STACK_SIZE 0x8000
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#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/
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#define SOF_STACK_BASE (DRAM_BASE + DRAM0_SIZE)
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#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE)
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/* Vector and literal sizes - not in core-isa.h */
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#define SOF_MEM_VECT_LIT_SIZE 0x4
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#define SOF_MEM_VECT_TEXT_SIZE 0x1c
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#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE)
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#define SOF_MEM_RESET_TEXT_SIZE 0x2e0
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#define SOF_MEM_RESET_LIT_SIZE 0x120
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#define SOF_MEM_VECBASE_LIT_SIZE 0x178
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#define SOF_MEM_RO_SIZE 0x8
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#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE
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/** \brief EDF task's default stack size in bytes. */
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#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072
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#if !defined(__ASSEMBLER__) && !defined(LINKER)
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struct sof;
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/**
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* \brief Data shared between different cores.
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* Does nothing, since mt8186 doesn't support SMP.
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*/
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#define SHARED_DATA
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void platform_init_memmap(struct sof *sof);
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static inline void *platform_shared_get(void *ptr, int bytes)
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{
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return ptr;
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}
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#define uncache_to_cache(address) address
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#define cache_to_uncache(address) address
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#define is_uncached(address) 0
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/**
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* \brief Function for keeping shared data synchronized.
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* It's used after usage of data shared by different cores.
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* Such data is either statically marked with SHARED_DATA
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* or dynamically allocated with SOF_MEM_FLAG_SHARED flag.
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* Does nothing, since mt8186 doesn't support SMP.
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*/
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static inline void *platform_rfree_prepare(void *ptr)
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{
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return ptr;
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}
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#endif
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#define host_to_local(addr) (addr)
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#define local_to_host(addr) (addr)
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#endif /* __PLATFORM_LIB_MEMORY_H__ */
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#else
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#error "This file shouldn't be included from outside of sof/lib/memory.h"
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||||
#endif /* __SOF_LIB_MEMORY_H__ */
|
||||
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Reference in New Issue