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Merge pull request #414 from tlauda/topic/slave_cores_vecbase 

arch: fix level 1 interrupts handling by slave cores
This commit is contained in:
Liam Girdwood 2018-09-25 20:43:06 +01:00 committed by GitHub
parent 92844ecc3b c6cc4cc70d
commit 2460b01627
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 15 additions and 49 deletions
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10
src/arch/xtensa/smp/xtos/crt1-boards.S
View File

@ -168,7 +168,6 @@ xtos_per_core:
writesr excsave 5 a4
#endif
xtos_per_core_cacheattr:
get_prid a5
#if PLATFORM_MASTER_CORE_ID == 0
beqz a5, xtos_per_core_obtain_xtos_structs
@ -176,6 +175,8 @@ xtos_per_core_cacheattr:
movi a4, PLATFORM_MASTER_CORE_ID
beq a5, a4, xtos_per_core_obtain_xtos_structs
#endif
xtos_per_core_cacheattr:
#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || \
XCHAL_HAVE_XLT_CACHEATTR || \
(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
@ -183,6 +184,13 @@ xtos_per_core_cacheattr:
cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */
#endif
xtos_per_core_vecbase:
#if XCHAL_HAVE_VECBASE
/* note: absolute symbol, not a ptr */
movi a2, _memmap_vecbase_reset
wsr.vecbase a2
#endif
// Obtain core structs from given address.
xtos_per_core_obtain_xtos_structs:
get_prid a5

2
src/arch/xtensa/smp/xtos/int-medpri-dispatcher.S
View File

@ -128,7 +128,7 @@ LABEL(_Level,FromVector):
// Change stack pointer
xtos_stack_addr_percore a13, _INTERRUPT_LEVEL, xtos_stack_for_interrupt
s32i a1, a13, 0
addi a1, a13, XTOS_STACK_FOR_INTERRUPT_SIZE
addi a1, a13, XTOS_INT_STACK_SIZE
/* Load the handler from the table, initialize two args (interrupt
* number and exception stack frame), then call the interrupt handler.

18
src/platform/apollolake/apollolake.x.in
View File

@ -165,24 +165,10 @@ ENTRY(_MainEntry)
_rom_store_table = 0;
/* ABI0 does not use Window base */
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
_memmap_cacheattr_wt_base = 0x11021000;
_memmap_cacheattr_bp_base = 0x22022000;
_memmap_cacheattr_unused_mask = 0x00F00FFF;
_memmap_cacheattr_wb_trapnull = 0x4422422F;
_memmap_cacheattr_wba_trapnull = 0x4422422F;
_memmap_cacheattr_wbna_trapnull = 0x25222222;
_memmap_cacheattr_wt_trapnull = 0x1122122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0x44F24FFF;
_memmap_cacheattr_wt_strict = 0x11F21FFF;
_memmap_cacheattr_bp_strict = 0x22F22FFF;
_memmap_cacheattr_wb_allvalid = 0x44224222;
_memmap_cacheattr_wt_allvalid = 0x11221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;
_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
SECTIONS

2
src/platform/apollolake/include/platform/memory.h
View File

@ -143,7 +143,7 @@
#define HEAP_SYSTEM_0_BASE \
(SOF_TEXT_BASE + SOF_TEXT_SIZE +\
SOF_DATA_SIZE + SOF_BSS_DATA_SIZE)
#define HEAP_SYSTEM_0_SIZE 0x8000
#define HEAP_SYSTEM_0_SIZE 0xa000
#define HEAP_SYSTEM_1_BASE (HEAP_SYSTEM_0_BASE + HEAP_SYSTEM_0_SIZE)
#define HEAP_SYSTEM_1_SIZE 0x1000

16
src/platform/cannonlake/cannonlake.x.in
View File

@ -161,24 +161,10 @@ ENTRY(_MainEntry)
_rom_store_table = 0;
/* ABI0 does not use Window base */
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
_memmap_cacheattr_wt_base = 0x11021000;
_memmap_cacheattr_bp_base = 0x22022000;
_memmap_cacheattr_unused_mask = 0x00F00FFF;
_memmap_cacheattr_wb_trapnull = 0x4422422F;
_memmap_cacheattr_wba_trapnull = 0x4422422F;
_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
_memmap_cacheattr_wt_trapnull = 0x1122122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0x44F24FFF;
_memmap_cacheattr_wt_strict = 0x11F21FFF;
_memmap_cacheattr_bp_strict = 0x22F22FFF;
_memmap_cacheattr_wb_allvalid = 0x44224222;
_memmap_cacheattr_wt_allvalid = 0x11221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
SECTIONS

16
src/platform/icelake/icelake.x.in
View File

@ -161,24 +161,10 @@ ENTRY(_MainEntry)
_rom_store_table = 0;
/* ABI0 does not use Window base */
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR);
PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x44024000;
_memmap_cacheattr_wt_base = 0x11021000;
_memmap_cacheattr_bp_base = 0x22022000;
_memmap_cacheattr_unused_mask = 0x00F00FFF;
_memmap_cacheattr_wb_trapnull = 0x4422422F;
_memmap_cacheattr_wba_trapnull = 0x4422422F;
_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
_memmap_cacheattr_wt_trapnull = 0x1122122F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0x44F24FFF;
_memmap_cacheattr_wt_strict = 0x11F21FFF;
_memmap_cacheattr_bp_strict = 0x22F22FFF;
_memmap_cacheattr_wb_allvalid = 0x44224222;
_memmap_cacheattr_wt_allvalid = 0x11221222;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
SECTIONS