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tgl: fix single-core building 

All TGL-based ADSPs are multicore, but it should also be possible to
build SOF with CONFIG_CORE_COUNT=1.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2022-04-06 12:02:33 +02:00 committed by Liam Girdwood
parent 5191c0ad26
commit 2238f3da32
1 changed files with 7 additions and 1 deletions
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8
src/platform/tigerlake/tigerlake.x.in
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@ -105,6 +105,7 @@ MEMORY
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
#if CONFIG_MULTICORE
lpsram_alt_reset_vec_seg :
org = LP_SRAM_ALT_RESET_VEC_BASE,
len = LP_SRAM_ALT_RESET_VEC_SIZE
@ -114,6 +115,7 @@ MEMORY
lpsram_code_seg :
org = LP_SRAM_CODE_BASE,
len = LP_SRAM_CODE_SIZE
#endif
lpsram_mem :
org = LP_SRAM_START,
len = LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE)
@ -374,6 +376,7 @@ SECTIONS
_etext = .;
} >sof_fw :sof_fw_phdr
#if CONFIG_MULTICORE
.AlternateResetVector.text : ALIGN(64)
{
_alternate_reset_vector_start = ABSOLUTE(.);
@ -397,6 +400,7 @@ SECTIONS
. = ALIGN(16);
_lpsram_code_end = ABSOLUTE(.);
} >lpsram_code_seg AT> sof_fw : lpsram_code_phdr
#endif
.rodata : ALIGN(4096)
{
@ -500,10 +504,12 @@ SECTIONS
LONG(LOADADDR(.AlternateResetVector.text));
LONG(ADDR(.AlternateResetVector.text));
LONG(SIZEOF(.AlternateResetVector.text));
#if CONFIG_MULTICORE
/* Entry 2 */
LONG(LOADADDR(.AlternateResetL2IntVector.text));
LONG(ADDR(.AlternateResetL2IntVector.text));
LONG(SIZEOF(.AlternateResetL2IntVector.text));
#endif
/* Entry 3 */
LONG(LOADADDR(.LpsramCode.text));
LONG(ADDR(.LpsramCode.text));
@ -556,12 +562,12 @@ SECTIONS
. = . + HEAP_SYSTEM_SHARED_SIZE;
. = ALIGN (PLATFORM_DCACHE_ALIGN);
_system_shared_heap_end = ABSOLUTE(.);
#endif
. = ALIGN (SRAM_BANK_SIZE);
_sof_core_s_start = ABSOLUTE(.);
. = . + SOF_CORE_S_T_SIZE;
_sof_core_s_end = ABSOLUTE(.);
#endif
. = ALIGN (SRAM_BANK_SIZE);
_runtime_heap_start = ABSOLUTE(.);