From 1a8c1235117c1031fc46a79c83fcb01e51761dee Mon Sep 17 00:00:00 2001 From: Pierre-Louis Bossart Date: Sat, 27 Jun 2020 14:11:18 -0500 Subject: [PATCH] topology: cht-rt5682: align with byt-codec topology Same parameters, so let's use the same template Signed-off-by: Pierre-Louis Bossart --- tools/topology/CMakeLists.txt | 2 +- tools/topology/sof-cht-rt5682.m4 | 71 -------------------------------- 2 files changed, 1 insertion(+), 72 deletions(-) delete mode 100644 tools/topology/sof-cht-rt5682.m4 diff --git a/tools/topology/CMakeLists.txt b/tools/topology/CMakeLists.txt index e2b2fab58..6b7452aae 100644 --- a/tools/topology/CMakeLists.txt +++ b/tools/topology/CMakeLists.txt @@ -21,7 +21,6 @@ set(TPLGS "sof-cht-nocodec\;sof-byt-nocodec\;-DPLATFORM=byt-nocodec\;-DSSP_NUM=2" "sof-bdw-nocodec\;sof-bdw-nocodec" "sof-cht-max98090\;sof-cht-max98090" - "sof-cht-rt5682\;sof-cht-rt5682" "sof-cht-src-50khz-pcm512x\;sof-cht-src-50khz-pcm512x" "sof-hda-generic\;sof-hda-generic\;-DCHANNELS=0\;-DPPROC=volume" "sof-hda-generic\;sof-hda-generic-2ch\;-DCHANNELS=2\;-DPPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4" @@ -59,6 +58,7 @@ set(TPLGS "sof-byt-codec\;sof-cht-rt5645\;-DCODEC=RT5645\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-byt-codec\;sof-cht-rt5651\;-DCODEC=RT5651\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-byt-codec\;sof-cht-rt5670\;-DCODEC=RT5670\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" + "sof-byt-codec\;sof-cht-rt5682\;-DCODEC=RT5682\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-byt-codec\;sof-cht-da7213\;-DCODEC=DA7213\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-byt-codec\;sof-cht-cx2072x\;-DCODEC=CX2072X\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" "sof-byt-codec\;sof-cht-es8316\;-DCODEC=ES8316\;-DPLATFORM=cht-codec\;-DSSP_NUM=2" diff --git a/tools/topology/sof-cht-rt5682.m4 b/tools/topology/sof-cht-rt5682.m4 deleted file mode 100644 index 24cde320f..000000000 --- a/tools/topology/sof-cht-rt5682.m4 +++ /dev/null @@ -1,71 +0,0 @@ -# -# Topology for generic CHT board with Realtek codecs -# - -# Include topology builder -include(`utils.m4') -include(`dai.m4') -include(`pipeline.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Cherrytrail DSP configuration -include(`platform/intel/cht.m4') - -# -# Define the pipelines -# -# PCM0 <----> Volume <----> SSP2 -# - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s24le. -# Set 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4, - 1, 0, 2, s24le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s24le. -# Set 1000us deadline on core 0 with priority 0 -PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4, - 2, 0, 2, s24le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAI configuration -# -# SSP port 2 is our only pipeline DAI -# - -# playback DAI is SSP2 using 2 periods -# Buffers use s24le format, 1000us deadline on core 0 with priority 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 2, SSP2-Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - -# capture DAI is SSP2 using 2 periods -# Buffers use s24le format, 1000us deadline on core 0 with priority 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 2, SSP2-Codec, - PIPELINE_SINK_2, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - -# PCM Low Latency -PCM_DUPLEX_ADD(SSP2, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) - -# -# BE configurations - overrides config in ACPI if present -# -DAI_CONFIG(SSP, 2, 0, SSP2-Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in), - SSP_CLOCK(bclk, 2400000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 25, 3, 3), - SSP_CONFIG_DATA(SSP, 2, 24)))