mirror of https://github.com/thesofproject/sof.git
topology1:renoir: add DTS + EQ topology
Add a new m4 to support DTS SDK -> EQ processing Signed-off-by: Joe.Cheng <joe.cheng@xperi.com>
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@ -21,7 +21,7 @@ include(`platform/amd/acp.m4')
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# Playback pipeline 1 on PCM 0 using max 2 channels of s16le.
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# Schedule 96 frames per 2000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(
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ifdef(`DTS', sof/pipe-eq-iir-dts-codec-playback.m4, sof/pipe-passthrough-playback.m4),
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ifdef(`DTS', sof/pipe-dts-codec-eq-iir-playback.m4, sof/pipe-passthrough-playback.m4),
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1, 0, 2, s16le,
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1000, 0, 0,
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48000, 48000, 48000)
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@ -0,0 +1,108 @@
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# Low Latency Passthrough with DTS codec Pipeline and PCM
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#
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# Pipeline Endpoints for connection are :-
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#
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# host PCM_P --> B0 --> DTS Codec --> B1 --> EQ 0 --> B2 --> sink DAI0
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# Include topology builder
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include(`utils.m4')
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include(`buffer.m4')
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include(`pcm.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`codec_adapter.m4')
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include(`bytecontrol.m4')
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include(`eq_iir.m4')
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#
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# Controls
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#
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#
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# DTS Codec
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#
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include(`dts_codec_adapter.m4')
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#
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# IIR EQ
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#
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define(DEF_EQIIR_COEF, concat(`eqiir_coef_', PIPELINE_ID))
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define(DEF_EQIIR_PRIV, concat(`eqiir_priv_', PIPELINE_ID))
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# define filter. eq_iir_coef_flat.m4 is set by default
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ifdef(`PIPELINE_FILTER1', , `define(PIPELINE_FILTER1, eq_iir_coef_flat.m4)')
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include(PIPELINE_FILTER1)
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# EQ Bytes control with max value of 255
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C_CONTROLBYTES(DEF_EQIIR_COEF, PIPELINE_ID,
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CONTROLBYTES_OPS(bytes, 258 binds the mixer control to bytes get/put handlers, 258, 258),
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CONTROLBYTES_EXTOPS(258 binds the mixer control to bytes get/put handlers, 258, 258),
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, , ,
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CONTROLBYTES_MAX(, 1024),
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,
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DEF_EQIIR_PRIV)
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#
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# Components and Buffers
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#
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ifdef(`CA_SCHEDULE_CORE',`', `define(`CA_SCHEDULE_CORE', `SCHEDULE_CORE')')
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# Host "Playback with codec adapter" PCM
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# with DAI_PERIODS sink and 0 source periods
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W_PCM_PLAYBACK(PCM_ID, Passthrough Playback, DAI_PERIODS, 0, SCHEDULE_CORE)
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W_CODEC_ADAPTER(0, PIPELINE_FORMAT, DAI_PERIODS, DAI_PERIODS, CA_SCHEDULE_CORE,
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LIST(` ', "CA_SETUP_CONTROLBYTES_NAME_PIPE"))
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# "EQ 0" has 2 sink period and 2 source periods
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W_EQ_IIR(0, PIPELINE_FORMAT, 2, 2, SCHEDULE_CORE,
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LIST(` ', "DEF_EQIIR_COEF"))
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# Playback Buffers
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W_BUFFER(0, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
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PLATFORM_HOST_MEM_CAP)
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W_BUFFER(1, COMP_BUFFER_SIZE(2,
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COMP_SAMPLE_SIZE(PIPELINE_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
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PLATFORM_HOST_MEM_CAP)
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W_BUFFER(2, COMP_BUFFER_SIZE(DAI_PERIODS,
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COMP_SAMPLE_SIZE(DAI_FORMAT), PIPELINE_CHANNELS, COMP_PERIOD_FRAMES(PCM_MAX_RATE, SCHEDULE_PERIOD)),
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PLATFORM_DAI_MEM_CAP)
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#
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# Pipeline Graph
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#
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# host PCM_P --> B0 --> DTS Codec --> B1 --> EQ 0 --> B2 --> sink DAI0
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P_GRAPH(pipe-pass-playback-PIPELINE_ID, PIPELINE_ID,
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LIST(` ',
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`dapm(N_BUFFER(0), N_PCMP(PCM_ID))',
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`dapm(N_CODEC_ADAPTER(0), N_BUFFER(0))',
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`dapm(N_BUFFER(1), N_CODEC_ADAPTER(0))',
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`dapm(N_EQ_IIR(0), N_BUFFER(1))',
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`dapm(N_BUFFER(2), N_EQ_IIR(0))'))
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#
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# Pipeline Source and Sinks
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#
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indir(`define', concat(`PIPELINE_SOURCE_', PIPELINE_ID), N_BUFFER(2))
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indir(`define', concat(`PIPELINE_PCM_', PIPELINE_ID), Passthrough Playback PCM_ID)
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#
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# PCM Configuration
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#
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PCM_CAPABILITIES(Passthrough Playback PCM_ID, CAPABILITY_FORMAT_NAME(PIPELINE_FORMAT), PCM_MIN_RATE, PCM_MAX_RATE, 2, PIPELINE_CHANNELS, 2, 16, 192, 16384, 65536, 65536)
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undefine(`CA_SETUP_CONTROLBYTES_NAME_PIPE')
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undefine(`CA_SETUP_PARAMS')
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undefine(`CA_SCHEDULE_CORE')
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undefine(`CA_SETUP_CONTROLBYTES_NAME')
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undefine(`CA_SETUP_CONTROLBYTES_MAX')
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undefine(`CA_SETUP_CONTROLBYTES')
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undefine(`DEF_EQIIR_COEF')
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undefine(`DEF_EQIIR_PRIV')
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