mirror of https://github.com/thesofproject/sof.git
platform: tigerlake: move remain use of shim.h to cavs code
The only remaining user of the SOF shim.h platform interface is Intel Tiger Lake platform. And even for this target, only a very small part of the interface is used. Everything else is either not used, and/or moved to Zephyr. Move the remaining definitions to the Tiger Lake implementation, allowing the interface to be removed from SOF platform layer. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
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@ -81,6 +81,17 @@ static const struct sof_ipc_fw_ready ready
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#define CAVS_DEFAULT_RO_FOR_MEM SHIM_CLKCTL_OCS_HP_RING
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#endif
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#include <cavs/drivers/sideband-ipc.h>
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/* DSP IPC for Host Registers */
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#define IPC_DIPCIDR 0x10
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#define IPC_DIPCIDD 0x18
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static inline void ipc_write(uint32_t reg, uint32_t val)
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{
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*((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val;
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}
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int platform_boot_complete(uint32_t boot_message)
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{
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struct ipc_cmd_hdr header;
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@ -12,263 +12,7 @@
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#ifndef __PLATFORM_LIB_SHIM_H__
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#define __PLATFORM_LIB_SHIM_H__
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#include <cavs/drivers/sideband-ipc.h>
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#include <cavs/lib/shim.h>
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#include <rtos/bit.h>
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#include <sof/lib/memory.h>
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/* DSP IPC for Host Registers */
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#define IPC_DIPCTDR 0x00
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#define IPC_DIPCTDA 0x04
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#define IPC_DIPCTDD 0x08
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#define IPC_DIPCIDR 0x10
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#define IPC_DIPCIDA 0x14
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#define IPC_DIPCIDD 0x18
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#define IPC_DIPCCTL 0x28
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#define IPC_DSP_OFFSET 0x10
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/* DSP IPC for intra DSP communication */
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#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET)
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#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET)
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#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET)
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#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET)
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#define IPC_IDCCTL 0x50
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/* IDCTFC */
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#define IPC_IDCTFC_BUSY BIT(31)
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#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
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/* IDCTEFC */
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#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
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/* IDCITC */
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#define IPC_IDCITC_BUSY BIT(31)
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#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
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/* IDCIETC */
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#define IPC_IDCIETC_DONE BIT(30)
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#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
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/* IDCCTL */
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#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x))
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#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
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#define IRQ_CPU_OFFSET 0x40
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#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET))
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/* all mask valid bits */
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#define REG_IRQ_IL2MD_ALL 0x03F181F0
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#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET))
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/* all mask valid bits */
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#define REG_IRQ_IL3MD_ALL 0x807F81FF
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#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET))
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/* all mask valid bits */
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#define REG_IRQ_IL4MD_ALL 0x807F81FF
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#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET))
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#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET))
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/* all mask valid bits */
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#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF
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#define REG_IRQ_IL2RSD 0x100
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#define REG_IRQ_IL3RSD 0x104
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#define REG_IRQ_IL4RSD 0x108
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#define REG_IRQ_IL5RSD 0x10c
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#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16)
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#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24)
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/* DSP Shim Registers */
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#define SHIM_DSPWC 0x20 /* DSP Wall Clock */
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#define SHIM_DSPWCL 0x20 /* DSP Wall Clock Low */
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#define SHIM_DSPWCH 0x24 /* DSP Wall Clock High */
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#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */
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#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */
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#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */
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#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */
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#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */
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#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */
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#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */
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/** \brief Clock control */
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#define SHIM_CLKCTL 0x78
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/** \brief Request HP RING Oscillator Clock */
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#define SHIM_CLKCTL_RHROSCC BIT(31)
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/** \brief Request WOVCRO Clock */
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#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4)
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/** \brief Request XTAL Oscillator Clock */
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#define SHIM_CLKCTL_RXOSCC BIT(30)
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/** \brief Request LP RING Oscillator Clock */
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#define SHIM_CLKCTL_RLROSCC BIT(29)
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/** \brief Tensilica Core Prevent Local Clock Gating */
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#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x))
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#define SHIM_CLKCTL_TCPLCG_DIS(x) 0
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#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \
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SHIM_CLKCTL_TCPLCG_DIS(1) | \
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SHIM_CLKCTL_TCPLCG_DIS(2) | \
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SHIM_CLKCTL_TCPLCG_DIS(3))
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/** \brief Oscillator Clock Select*/
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#define SHIM_CLKCTL_OCS_HP_RING BIT(2)
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#define SHIM_CLKCTL_OCS_LP_RING 0
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#define SHIM_CLKCTL_WOVCROSC BIT(3)
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/** \brief LP Memory Clock Select */
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#define SHIM_CLKCTL_LMCS_DIV2 0
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#define SHIM_CLKCTL_LMCS_DIV4 BIT(1)
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/** \brief HP Memory Clock Select */
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#define SHIM_CLKCTL_HMCS_DIV2 0
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#define SHIM_CLKCTL_HMCS_DIV4 BIT(0)
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/* Core clock PLL divisor */
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#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2)
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/* Prevent Audio PLL Shutdown */
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#define SHIM_CLKCTL_TCPAPLLS BIT(7)
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/* 0--from PLL, 1--from oscillator */
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#define SHIM_CLKCTL_HDCS BIT(4)
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/* Oscillator select */
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#define SHIM_CLKCTL_HDOCS BIT(2)
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/* HP memory clock PLL divisor */
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#define SHIM_CLKCTL_HPMPCS BIT(0)
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/** \brief Mask for requesting clock
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*/
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#define SHIM_CLKCTL_OSC_REQUEST_MASK \
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(SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \
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SHIM_CLKCTL_RLROSCC)
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/** \brief Mask for setting previously requested clock
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*/
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#define SHIM_CLKCTL_OSC_SOURCE_MASK \
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(SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \
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SHIM_CLKCTL_HMCS_DIV4)
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/** \brief Clock status */
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#define SHIM_CLKSTS 0x7C
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/** \brief HP RING Oscillator Clock Status */
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#define SHIM_CLKSTS_HROSCCS BIT(31)
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/** \brief WOVCRO Clock Status */
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#define SHIM_CLKSTS_WOV_CRO BIT(4)
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/** \brief XTAL Oscillator Clock Status */
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#define SHIM_CLKSTS_XOSCCS BIT(30)
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/** \brief LP RING Oscillator Clock Status */
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#define SHIM_CLKSTS_LROSCCS BIT(29)
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#define SHIM_PWRCTL 0x90
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#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x)
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#define SHIM_PWRCTL_TCPCTLPG BIT(4)
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#define SHIM_PWRSTS 0x92
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#define SHIM_LPSCTL 0x94
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#define SHIM_LPSCTL_BID BIT(7)
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#define SHIM_LPSCTL_FDSPRUN BIT(9)
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#define SHIM_LPSCTL_BATTR_0 BIT(12)
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/** \brief GPDMA shim registers Control */
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#define SHIM_GPDMA_BASE_OFFSET 0x6500
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#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100)
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/** \brief GPDMA Clock Control */
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#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4)
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/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
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#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
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/** \brief GPDMA Channel Linear Link Position Control */
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#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10)
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#define SHIM_GPDMA_CHLLPC_EN BIT(7)
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#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
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#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10)
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#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10)
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/* I2S SHIM Registers */
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#define I2SLCTL 0x71C04
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/* SPA register should be set for each I2S port and DSP should
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* wait for CPA to be set
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*/
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#define I2SLCTL_SPA(x) BIT(0 + x)
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#define I2SLCTL_CPA(x) BIT(8 + x)
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#define SHIM_L2_MECS (SHIM_BASE + 0xd0)
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/** \brief LDO Control */
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#define SHIM_LDOCTL 0xA4
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#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16)
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#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
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#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
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#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16))
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#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
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#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0)
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#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2)
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#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
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#define LPGPDMA_CTLOSEL_FLAG BIT(15)
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#define LPGPDMA_CHOSEL_FLAG 0xFF
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#define DSP_INIT_IOPO 0x71A68
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#define IOPO_DMIC_FLAG BIT(0)
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#define IOPO_I2S_FLAG MASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8)
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#define DSP_INIT_GENO 0x71A6C
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#define GENO_MDIVOSEL BIT(1)
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#define GENO_DIOPTOSEL BIT(2)
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#define DSP_INIT_ALHO 0x71A70
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#define ALHO_ASO_FLAG BIT(0)
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#define ALHO_CSO_FLAG BIT(1)
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#define ALHO_CFO_FLAG BIT(2)
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#define SHIM_SVCFG 0xF4
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#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1)
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/* host windows */
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#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0)
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#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4)
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#define DMWBA_ENABLE BIT(0)
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#define DMWBA_READONLY BIT(1)
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/* DMIC power ON bit */
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#define DMICLCTL_SPA ((uint32_t) BIT(0))
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/* DMIC disable clock gating */
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#define DMIC_DCGD ((uint32_t) BIT(30))
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/* no-op */
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#endif /* __PLATFORM_LIB_SHIM_H__ */
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@ -9,6 +9,40 @@
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#include <sof/drivers/ssp.h>
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#include <rtos/clk.h>
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/** \brief Request HP RING Oscillator Clock */
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#define SHIM_CLKCTL_RHROSCC BIT(31)
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/** \brief Request WOVCRO Clock */
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#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4)
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/** \brief Request LP RING Oscillator Clock */
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#define SHIM_CLKCTL_RLROSCC BIT(29)
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/** \brief Oscillator Clock Select*/
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#define SHIM_CLKCTL_OCS_HP_RING BIT(2)
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#define SHIM_CLKCTL_OCS_LP_RING 0
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#define SHIM_CLKCTL_WOVCROSC BIT(3)
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/** \brief LP Memory Clock Select */
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#define SHIM_CLKCTL_LMCS_DIV2 0
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#define SHIM_CLKCTL_LMCS_DIV4 BIT(1)
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/** \brief HP Memory Clock Select */
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#define SHIM_CLKCTL_HMCS_DIV2 0
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#define SHIM_CLKCTL_HMCS_DIV4 BIT(0)
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/** \brief HP RING Oscillator Clock Status */
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#define SHIM_CLKSTS_HROSCCS BIT(31)
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/** \brief WOVCRO Clock Status */
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#define SHIM_CLKSTS_WOV_CRO BIT(4)
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/** \brief XTAL Oscillator Clock Status */
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#define SHIM_CLKSTS_XOSCCS BIT(30)
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/** \brief LP RING Oscillator Clock Status */
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#define SHIM_CLKSTS_LROSCCS BIT(29)
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static const struct freq_table platform_cpu_freq[] = {
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{ 38400000, 38400 },
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{ 120000000, 120000 },
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