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platform: mt8186: Change ADSP max clock frequency 

Change the maximum frequency to 300M because power issue.
The mt8186 supports 800M/400M/300M frequencies, each requires
0.8/0.7/0.65 minimum core voltages. The 300M is the most
compatible option because it has the lowest minimum core voltage.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
This commit is contained in:
Tinghan Shen 2022-11-02 20:19:13 +08:00 committed by Liam Girdwood
parent d259d1bd59
commit 161e6b7b1a
2 changed files with 13 additions and 19 deletions
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11
src/platform/mt8186/include/platform/lib/clk.h
View File

@ -18,9 +18,10 @@ struct sof;
#define CLK_CPU(x) (x)
#define CLK_DEFAULT_CPU_HZ 26000000
#define CLK_MAX_CPU_HZ 800000000
/* check vcore voltage before select higher frequency than 300M */
#define CLK_MAX_CPU_HZ 300000000
#define NUM_CLOCKS 1
#define NUM_CPU_FREQ 5
#define NUM_CPU_FREQ 3
/* MTK_ADSP_CLK_BUS_UPDATE */
#define MTK_ADSP_CLK_BUS_UPDATE_BIT BIT(31)
@ -46,10 +47,8 @@ struct sof;
/* 0 is the lowest request */
enum ADSP_HW_DSP_CLK {
ADSP_CLK_26M = 0,
ADSP_CLK_PLL_800M_D_8,
ADSP_CLK_PLL_800M_D_4,
ADSP_CLK_PLL_800M_D_2,
ADSP_CLK_PLL_800M,
ADSP_CLK_PLL_300M,
ADSP_CLK_PLL_400M,
};
void platform_clock_init(struct sof *sof);

21
src/platform/mt8186/lib/clk.c
View File

@ -26,10 +26,8 @@ DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_uuid), LOG_LEVEL_INFO);
/* default voltage is 0.8V */
const struct freq_table platform_cpu_freq[] = {
{ 26000000, 26000},
{ 100000000, 26000},
{ 200000000, 26000},
{ 300000000, 26000},
{ 400000000, 26000},
{ 800000000, 26000},
};
STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
@ -62,20 +60,17 @@ static int clock_platform_set_dsp_freq(int clock, int freq_idx)
case ADSP_CLK_26M:
set_mux_adsp_sel(MTK_CLK_ADSP_26M);
break;
case ADSP_CLK_PLL_800M_D_8:
set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_8);
case ADSP_CLK_PLL_300M:
clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
break;
case ADSP_CLK_PLL_800M_D_4:
set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_4);
break;
case ADSP_CLK_PLL_800M_D_2:
set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_2);
break;
case ADSP_CLK_PLL_800M:
case ADSP_CLK_PLL_400M:
clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
break;
default:
set_mux_adsp_sel(MTK_CLK_ADSP_26M);
clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
tr_err(&clkdrv_tr, "unknown freq index %x\n", freq_idx);
break;
}