mirror of https://github.com/thesofproject/sof.git
platform: mt8186: Change ADSP max clock frequency
Change the maximum frequency to 300M because power issue. The mt8186 supports 800M/400M/300M frequencies, each requires 0.8/0.7/0.65 minimum core voltages. The 300M is the most compatible option because it has the lowest minimum core voltage. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
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@ -18,9 +18,10 @@ struct sof;
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#define CLK_CPU(x) (x)
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#define CLK_DEFAULT_CPU_HZ 26000000
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#define CLK_MAX_CPU_HZ 800000000
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/* check vcore voltage before select higher frequency than 300M */
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#define CLK_MAX_CPU_HZ 300000000
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#define NUM_CLOCKS 1
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#define NUM_CPU_FREQ 5
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#define NUM_CPU_FREQ 3
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/* MTK_ADSP_CLK_BUS_UPDATE */
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#define MTK_ADSP_CLK_BUS_UPDATE_BIT BIT(31)
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@ -46,10 +47,8 @@ struct sof;
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/* 0 is the lowest request */
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enum ADSP_HW_DSP_CLK {
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ADSP_CLK_26M = 0,
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ADSP_CLK_PLL_800M_D_8,
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ADSP_CLK_PLL_800M_D_4,
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ADSP_CLK_PLL_800M_D_2,
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ADSP_CLK_PLL_800M,
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ADSP_CLK_PLL_300M,
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ADSP_CLK_PLL_400M,
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};
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void platform_clock_init(struct sof *sof);
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@ -26,10 +26,8 @@ DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_uuid), LOG_LEVEL_INFO);
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/* default voltage is 0.8V */
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const struct freq_table platform_cpu_freq[] = {
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{ 26000000, 26000},
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{ 100000000, 26000},
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{ 200000000, 26000},
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{ 300000000, 26000},
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{ 400000000, 26000},
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{ 800000000, 26000},
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};
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STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
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@ -62,20 +60,17 @@ static int clock_platform_set_dsp_freq(int clock, int freq_idx)
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case ADSP_CLK_26M:
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set_mux_adsp_sel(MTK_CLK_ADSP_26M);
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break;
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case ADSP_CLK_PLL_800M_D_8:
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set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_8);
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case ADSP_CLK_PLL_300M:
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clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
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set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
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break;
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case ADSP_CLK_PLL_800M_D_4:
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set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_4);
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break;
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case ADSP_CLK_PLL_800M_D_2:
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set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_2);
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break;
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case ADSP_CLK_PLL_800M:
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case ADSP_CLK_PLL_400M:
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clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
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set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
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break;
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default:
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set_mux_adsp_sel(MTK_CLK_ADSP_26M);
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clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
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tr_err(&clkdrv_tr, "unknown freq index %x\n", freq_idx);
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break;
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}
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