mirror of https://github.com/thesofproject/sof.git
pm_memory: add functionality to handle also LP SRAM
Refactors pm_memory in order to add functionality to also power gate LP SRAM in a similar fashion. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
This commit is contained in:
Tomasz Lauda
Tomasz Lauda
parent
91bdf1a5de
commit
11265e3e4f
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@ -14,6 +14,8 @@
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#ifndef __CAVS_LIB_PM_MEMORY_H__
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#define __CAVS_LIB_PM_MEMORY_H__
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#include <config.h>
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#include <stdbool.h>
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#include <stdint.h>
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/** \brief Memory banks pm masks data. */
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@ -31,16 +33,51 @@ struct ebb_data {
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};
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/**
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* \brief Set power gating of memory banks in the address range
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* \brief Sets HP SRAM enabled gating hw bit mask for memory banks.
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* \param[in] start_bank_id Id of first bank to be managed (inclusive) 0 based.
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* \param[in] ending_bank_id Id of last bank to be managed (inclusive) 0 based.
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* \param[in] enabled Deciding banks desired state (true powered false gated).
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*/
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void cavs_pm_memory_hp_sram_banks_power_gate(uint32_t start_bank_id,
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uint32_t ending_bank_id,
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bool enabled);
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/**
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* \brief Sets HP SRAM power gating.
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*
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* Power gates address range only on full banks if given address form mid block
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* it will try to narrow down power gate to nearest full banks
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* Power gates address range only on full banks. If given address form mid block
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* it will try to narrow down power gate to nearest full banks.
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*
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* \param[in] ptr Ptr to address from which to start gating.
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* \param[in] size Size of memory to manage.
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* \param[in] enabled Boolean deciding banks desired state (1 powered 0 gated).
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* \param[in] enabled Deciding banks desired state (true powered false gated).
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*/
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void set_power_gate_for_memory_address_range(void *ptr, uint32_t size,
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uint32_t enabled);
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void cavs_pm_memory_hp_sram_power_gate(void *ptr, uint32_t size, bool enabled);
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#if CONFIG_LP_SRAM
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/**
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* \brief Sets LP SRAM enabled gating hw bit mask for memory banks.
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* \param[in] start_bank_id Id of first bank to be managed (inclusive) 0 based.
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* \param[in] ending_bank_id Id of last bank to be managed (inclusive) 0 based.
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* \param[in] enabled Deciding banks desired state (true powered false gated).
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*/
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void cavs_pm_memory_lp_sram_banks_power_gate(uint32_t start_bank_id,
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uint32_t ending_bank_id,
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bool enabled);
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/**
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* \brief Sets LP SRAM power gating.
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*
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* Power gates address range only on full banks. If given address form mid block
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* it will try to narrow down power gate to nearest full banks.
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*
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* \param[in] ptr Ptr to address from which to start gating.
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* \param[in] size Size of memory to manage.
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* \param[in] enabled Deciding banks desired state (true powered false gated).
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*/
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void cavs_pm_memory_lp_sram_power_gate(void *ptr, uint32_t size, bool enabled);
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#endif /* CONFIG_LP_SRAM */
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#endif /* __CAVS_LIB_PM_MEMORY_H__ */
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@ -15,6 +15,8 @@
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#include <sof/lib/wait.h>
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#include <sof/trace/trace.h>
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#include <user/trace.h>
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#include <config.h>
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#include <stdbool.h>
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#include <stdint.h>
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/* 14f25ab6-3a4b-4e5d-b343-2a142d4e4d92 */
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@ -27,6 +29,41 @@ DECLARE_TR_CTX(pm_mem_tr, SOF_UUID(pm_mem_uuid), LOG_LEVEL_INFO);
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#define EBB_SEGMENT_SIZE_ZERO_BASE (EBB_SEGMENT_SIZE - 1)
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#define MEMORY_POWER_DOWN_DELAY 256
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/**
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* \brief Retrieves memory banks based on start and end pointer.
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* \param[in,out] start Start address of memory range.
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* \param[in,out] end End address of memory range.
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* \param[in] base Base address of memory range.
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* \param[in,out] start_bank Start bank id calculated by this function.
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* \param[in,out] end_bank End bank id calculated by this function.
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*/
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static void memory_banks_get(void *start, void *end, uint32_t base,
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uint32_t *start_bank, uint32_t *end_bank)
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{
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/* if ptr is not aligned to bank size change it to
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* closest possible memory address at the start of bank
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* or end for end address
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*/
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if ((uintptr_t)start % SRAM_BANK_SIZE)
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start = (void *)ALIGN((uintptr_t)start, SRAM_BANK_SIZE);
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if ((uintptr_t)end % SRAM_BANK_SIZE)
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end = (void *)ALIGN_DOWN((uintptr_t)end, SRAM_BANK_SIZE);
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/* return if no full bank could be found for enabled gate control */
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if ((char *)end - (char *)start < SRAM_BANK_SIZE) {
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tr_info(&pm_mem_tr, "cavs_pm_memory_banks_get(): cannot find full bank to perform gating operation");
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return;
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}
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*start_bank = ((uintptr_t)start - base) / SRAM_BANK_SIZE;
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/* Ending bank id has to be lowered by one because it is
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* calculated from memory end ptr
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*/
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*end_bank = ((uintptr_t)end - base) / SRAM_BANK_SIZE - 1;
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}
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/**
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* \brief Read masks from hw registers and prepare new masks from data
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* \param[in] ebb_data All masks data required for calculations.
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@ -137,16 +174,11 @@ static void write_new_masks_and_check_status(struct ebb_data *ebb)
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idelay(MEMORY_POWER_DOWN_DELAY);
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}
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/**
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* \brief Set memory enabled gating hw bit mask for memory banks
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* \param[in] start_bank_id Id of first bank to be managed (inclusive) 0 based.
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* \param[in] ending_bank_id Id of last bank to be managed (inclusive) 0 based.
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* \param[in] enabled Boolean deciding banks desired state (1 powered 0 gated).
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*/
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static void set_banks_gating(uint32_t start_bank_id, uint32_t ending_bank_id,
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uint32_t enabled)
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void cavs_pm_memory_hp_sram_banks_power_gate(uint32_t start_bank_id,
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uint32_t ending_bank_id,
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bool enabled)
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{
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struct ebb_data ebb = {0};
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struct ebb_data ebb = { 0 };
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ebb.start_bank_id = start_bank_id;
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ebb.ending_bank_id = ending_bank_id;
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@ -170,37 +202,51 @@ static void set_banks_gating(uint32_t start_bank_id, uint32_t ending_bank_id,
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shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS);
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}
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void set_power_gate_for_memory_address_range(void *ptr,
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uint32_t size, uint32_t enabled)
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void cavs_pm_memory_hp_sram_power_gate(void *ptr, uint32_t size, bool enabled)
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{
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uint32_t start_bank_id;
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uint32_t ending_bank_id;
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void *end_ptr = (char *)ptr + size;
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uint32_t start_bank = 0;
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uint32_t end_bank = 0;
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/* if ptr is not aligned to bank size change it to
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* closest possible memory address at the start of bank
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* or end for end address
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*/
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if ((uintptr_t)ptr % SRAM_BANK_SIZE)
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ptr = (void *)ALIGN((uintptr_t)ptr, SRAM_BANK_SIZE);
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memory_banks_get(ptr, (char *)ptr + size, HP_SRAM_BASE, &start_bank,
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&end_bank);
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if ((uintptr_t)end_ptr % SRAM_BANK_SIZE)
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end_ptr = (void *)ALIGN_DOWN((uintptr_t)ptr, SRAM_BANK_SIZE);
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/* return if no full bank could be found for enabled gate control */
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if ((char *)end_ptr - (char *)ptr < SRAM_BANK_SIZE) {
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tr_info(&pm_mem_tr, "Could not find full bank to perform gating operation");
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return;
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}
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start_bank_id = ((uintptr_t)ptr - HP_SRAM_BASE) / SRAM_BANK_SIZE;
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/* Ending bank id has to be lowered by one because it is
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* calculated from memory end ptr
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*/
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ending_bank_id = ((uintptr_t)end_ptr - HP_SRAM_BASE)
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/ SRAM_BANK_SIZE - 1;
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set_banks_gating(start_bank_id, ending_bank_id, enabled);
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cavs_pm_memory_hp_sram_banks_power_gate(start_bank, end_bank, enabled);
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}
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#endif
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#if CONFIG_LP_SRAM
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void cavs_pm_memory_lp_sram_banks_power_gate(uint32_t start_bank_id,
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uint32_t ending_bank_id,
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bool enabled)
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{
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uint32_t mask = MASK(ending_bank_id, start_bank_id);
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uint32_t expected = enabled ? 0 : mask;
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shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON);
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idelay(MEMORY_POWER_DOWN_DELAY);
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io_reg_update_bits(LSPGCTL, mask, enabled ? 0 : mask);
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idelay(MEMORY_POWER_DOWN_DELAY);
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while ((io_reg_read(LSPGISTS) & mask) != expected)
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idelay(MEMORY_POWER_DOWN_DELAY);
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shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS);
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}
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void cavs_pm_memory_lp_sram_power_gate(void *ptr, uint32_t size, bool enabled)
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{
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uint32_t start_bank = 0;
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uint32_t end_bank = 0;
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memory_banks_get(ptr, (char *)ptr + size, LP_SRAM_BASE, &start_bank,
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&end_bank);
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cavs_pm_memory_lp_sram_banks_power_gate(start_bank, end_bank, enabled);
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}
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#endif /* CONFIG_LP_SRAM */
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#endif /* CAVS_VERSION >= CAVS_VERSION_1_8 */
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@ -313,8 +313,8 @@ static inline void cavs_pm_runtime_core_dis_memory(uint32_t index)
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core_memory_ptr = (char *)&_sof_core_s_start
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+ (index - 1) * SOF_CORE_S_SIZE;
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set_power_gate_for_memory_address_range(core_memory_ptr,
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SOF_CORE_S_SIZE, 0);
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cavs_pm_memory_hp_sram_power_gate(core_memory_ptr, SOF_CORE_S_SIZE,
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false);
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#endif
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}
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@ -331,8 +331,8 @@ static inline void cavs_pm_runtime_core_en_memory(uint32_t index)
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core_memory_ptr = (char *)&_sof_core_s_start
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+ (index - 1) * SOF_CORE_S_SIZE;
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set_power_gate_for_memory_address_range(core_memory_ptr,
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SOF_CORE_S_SIZE, 1);
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cavs_pm_memory_hp_sram_power_gate(core_memory_ptr, SOF_CORE_S_SIZE,
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true);
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#endif
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}
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