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topology: sof-apl-wm8804: add capture support 

Add duplex capture - tested w/ HifiBerry Digi+

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
This commit is contained in:
Pierre-Louis Bossart 2020-04-16 19:26:53 -05:00 committed by Liam Girdwood
parent c57fe274fc
commit 0de9dfeeee
1 changed files with 16 additions and 2 deletions
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18
tools/topology/sof-apl-wm8804.m4
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@ -20,7 +20,7 @@ include(`platform/intel/bxt.m4')
# #
# Define the pipelines # Define the pipelines
# #
# PCM0 ----> volume -----> SSP5 (wm8804) # PCM0 <----> volume <-----> SSP5 (wm8804)
# #
dnl PIPELINE_PCM_ADD(pipeline, dnl PIPELINE_PCM_ADD(pipeline,
@ -36,6 +36,13 @@ PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
1000, 0, 0, 1000, 0, 0,
48000, 48000, 48000) 48000, 48000, 48000)
# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le.
# 1000us deadline on core 0 with priority 0
PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4,
2, 0, 2, s32le,
1000, 0, 0,
48000, 48000, 48000)
# #
# DAIs configuration # DAIs configuration
# #
@ -52,8 +59,15 @@ DAI_ADD(sof/pipe-dai-playback.m4,
PIPELINE_SOURCE_1, 2, s24le, PIPELINE_SOURCE_1, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
# capture DAI is SSP5 using 2 periods
# Buffers use s24le format, 1000us deadline on core 0 with priority 0
DAI_ADD(sof/pipe-dai-capture.m4,
2, SSP, 5, SSP5-Codec,
PIPELINE_SINK_2, 2, s24le,
1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA)
# PCM Low Latency, id 0 # PCM Low Latency, id 0
PCM_PLAYBACK_ADD(Port5, 0, PIPELINE_PCM_1) PCM_DUPLEX_ADD(Port5, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
# #
# BE configurations - overrides config in ACPI if present # BE configurations - overrides config in ACPI if present