mirror of https://github.com/thesofproject/sof.git
ipc: cnl: Add support for IPC on cannonlake
Support IPC on Intel Cannonlake platform. Signed-off-by: Rander Wang <rander.wang@linux.intel.com>
This commit is contained in:
Rander Wang
Liam Girdwood
parent
44c7093525
commit
0d09139b05
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@ -42,6 +42,14 @@ libipc_a_SOURCES = \
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dma-copy.c
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endif
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if BUILD_CANNONLAKE
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libipc_a_SOURCES = \
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ipc.c \
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intel-ipc.c \
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cnl-ipc.c \
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dma-copy.c
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endif
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libipc_a_CFLAGS = \
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$(ARCH_CFLAGS) \
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$(ARCH_INCDIR) \
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@ -0,0 +1,212 @@
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/*
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* Copyright (c) 2017, Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Intel Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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* Keyon Jie <yang.jie@linux.intel.com>
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Rander Wang <rander.wang@intel.com>
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*/
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#include <reef/debug.h>
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#include <reef/timer.h>
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#include <reef/interrupt.h>
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#include <reef/ipc.h>
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#include <reef/mailbox.h>
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#include <reef/reef.h>
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#include <reef/stream.h>
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#include <reef/dai.h>
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#include <reef/dma.h>
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#include <reef/alloc.h>
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#include <reef/wait.h>
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#include <reef/trace.h>
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#include <reef/ssp.h>
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#include <platform/interrupt.h>
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#include <platform/mailbox.h>
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#include <platform/shim.h>
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#include <platform/dma.h>
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#include <platform/platform.h>
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#include <reef/audio/component.h>
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#include <reef/audio/pipeline.h>
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#include <uapi/ipc.h>
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#include <reef/intel-ipc.h>
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extern struct ipc *_ipc;
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/* test code to check working IRQ */
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static void irq_handler(void *arg)
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{
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uint32_t dipctdr;
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uint32_t dipcida;
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uint32_t msg = 0;
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trace_ipc("IRQ");
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dipctdr = ipc_read(IPC_DIPCTDR);
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dipcida = ipc_read(IPC_DIPCIDA);
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/* new message from host */
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if (dipctdr & IPC_DIPCTDR_BUSY) {
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trace_ipc("Nms");
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/* mask Busy interrupt */
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ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCTBIE);
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msg = dipctdr & IPC_DIPCTDR_MSG_MASK;
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/* TODO: place message in Q and process later */
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/* It's not Q ATM, may overwrite */
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if (_ipc->host_pending)
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trace_ipc_error("Pen");
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_ipc->host_msg = msg;
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_ipc->host_pending = 1;
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}
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/* reply message(done) from host */
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if (dipcida & IPC_DIPCIDA_DONE) {
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trace_ipc("Rpy");
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/* mask Done interrupt */
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ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) & ~IPC_DIPCCTL_IPCIDIE);
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/* clear DONE bit - tell host we have completed the operation */
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ipc_write(IPC_DIPCIDA, ipc_read(IPC_DIPCIDA) |IPC_DIPCIDA_DONE);
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/* unmask Done interrupt */
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ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCIDIE);
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}
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}
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void ipc_platform_do_cmd(struct ipc *ipc)
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{
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struct intel_ipc_data *iipc = ipc_get_drvdata(ipc);
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struct sof_ipc_reply reply;
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int32_t err;
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trace_ipc("Cmd");
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/* perform command and return any error */
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err = ipc_cmd();
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if (err > 0) {
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goto done; /* reply created and copied by cmd() */
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} else if (err < 0) {
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/* send std error reply */
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reply.error = err;
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} else if (err == 0) {
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/* send std reply */
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reply.error = 0;
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}
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/* send std error/ok reply */
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reply.hdr.cmd = SOF_IPC_GLB_REPLY;
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reply.hdr.size = sizeof(reply);
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mailbox_hostbox_write(0, &reply, sizeof(reply));
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done:
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ipc->host_pending = 0;
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/* write 1 to clear busy, and trigger interrupt to host*/
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ipc_write(IPC_DIPCTDR, ipc_read(IPC_DIPCTDR) |IPC_DIPCTDR_BUSY);
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ipc_write(IPC_DIPCTDA, ipc_read(IPC_DIPCTDA) |IPC_DIPCTDA_BUSY );
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/* unmask Busy interrupt */
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ipc_write(IPC_DIPCCTL, ipc_read(IPC_DIPCCTL) | IPC_DIPCCTL_IPCTBIE);
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// TODO: signal audio work to enter D3 in normal context
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/* are we about to enter D3 ? */
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if (iipc->pm_prepare_D3) {
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while (1)
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wait_for_interrupt(0);
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}
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tracev_ipc("CmD");
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}
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void ipc_platform_send_msg(struct ipc *ipc)
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{
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struct ipc_msg *msg;
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uint32_t flags;
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spin_lock_irq(&ipc->lock, flags);
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/* any messages to send ? */
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if (list_is_empty(&ipc->msg_list)) {
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ipc->dsp_pending = 0;
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goto out;
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}
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/* now send the message */
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msg = list_first_item(&ipc->msg_list, struct ipc_msg, list);
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mailbox_dspbox_write(0, msg->tx_data, msg->tx_size);
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list_item_del(&msg->list);
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ipc->dsp_msg = msg;
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tracev_ipc("Msg");
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/* now interrupt host to tell it we have message sent */
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ipc_write(IPC_DIPCIDD, 0);
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ipc_write(IPC_DIPCIDR, 0x80000000 | msg->header);
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out:
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spin_unlock_irq(&ipc->lock, flags);
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}
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int platform_ipc_init(struct ipc *ipc)
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{
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struct intel_ipc_data *iipc;
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int i;
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_ipc = ipc;
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/* init ipc data */
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iipc = rzalloc(RZONE_SYS, RFLAGS_NONE, sizeof(struct intel_ipc_data));
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ipc_set_drvdata(_ipc, iipc);
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_ipc->dsp_msg = NULL;
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list_init(&ipc->empty_list);
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list_init(&ipc->msg_list);
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spinlock_init(&ipc->lock);
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for (i = 0; i < MSG_QUEUE_SIZE; i++)
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list_item_prepend(&ipc->message[i].list, &ipc->empty_list);
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/* allocate page table buffer */
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iipc->page_table = rballoc(RZONE_SYS, RFLAGS_NONE,
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HOST_PAGE_SIZE);
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if (iipc->page_table)
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bzero(iipc->page_table, HOST_PAGE_SIZE);
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/* dma */
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iipc->dmac0 = dma_get(DMA_GP_LP_DMAC0);
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/* PM */
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iipc->pm_prepare_D3 = 0;
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/* configure interrupt */
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interrupt_register(PLATFORM_IPC_INTERUPT, irq_handler, NULL);
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interrupt_enable(PLATFORM_IPC_INTERUPT);
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/* enable IPC interrupts from host */
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ipc_write(IPC_DIPCCTL, IPC_DIPCCTL_IPCIDIE | IPC_DIPCCTL_IPCTBIE);
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return 0;
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}
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