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platform: tigerlake: remove CAVS_LPS support 

Remove support for Intel cAVS Low Power Sequencer for Power Management.
This code is specific to XTOS builds for Tiger Lake (cAVS)
platforms and no longer used in Zephyr builds.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit is contained in:
Kai Vehmanen 2023-08-21 18:12:18 +03:00 committed by Kai Vehmanen
parent ba05d6b507
commit 0b79666a6d
10 changed files with 0 additions and 356 deletions
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6
src/ipc/ipc3/handler.c
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@ -784,9 +784,6 @@ static int ipc_pm_gate(uint32_t header)
if (pm_gate.flags & SOF_PM_PPG) {
pm_runtime_disable(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID);
#if (CONFIG_CAVS_LPS)
cpu_restore_secondary_cores();
#endif
} else {
/* before we enable pm runtime and perform D0->D0ix flow
* (primary core powers off secondary cores in
@ -794,9 +791,6 @@ static int ipc_pm_gate(uint32_t header)
* cores data for powering off (disable interrupt, perform
* cache writeback).
*/
#if (CONFIG_CAVS_LPS)
cpu_secondary_cores_prepare_d0ix();
#endif
pm_runtime_enable(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID);
}

9
src/platform/Kconfig
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@ -356,15 +356,6 @@ config L1_DRAM_MEMORY_BANK_SIZE
Specifies DRAM block size.
It can be used to calculate DRAM size.
config CAVS_LPS
bool "Intel cAVS Low Power Sequencer for Power Management"
depends on CAVS
default n
help
Select this to enable Intel cAVS Low Power Sequencer.
This option is required to support S0ix/D0ix mode
on cAVS platforms.
config CAVS_USE_LPRO_IN_WAITI
bool "Use low power ring oscillator in WFI"
default n

13
src/platform/intel/cavs/CMakeLists.txt
View File

@ -2,19 +2,6 @@
add_subdirectory(lib)
if(CONFIG_CAVS_LPS)
add_library(lps_vector STATIC "")
target_link_libraries(lps_vector sof_options)
target_compile_options(lps_vector PRIVATE -mtext-section-literals)
add_local_sources(lps_vector lps_pic_restore_vector.S)
target_link_libraries(sof_static_libraries INTERFACE lps_vector)
add_local_sources(sof lps_wait.c)
endif()
add_local_sources(sof platform.c)
target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/include)

109
src/platform/intel/cavs/include/cavs/lib/asm_ldo_management.h
View File

@ -1,109 +0,0 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright(c) 2018 Intel Corporation. All rights reserved.
*
* Author: Lech Betlej <lech.betlej@linux.intel.com>
*/
/**
* \file
* \brief Macros for controlling LDO state specific for cAVS
* \author Lech Betlej <lech.betlej@linux.intel.com>
*/
#ifndef __CAVS_LIB_ASM_LDO_MANAGEMENT_H__
#define __CAVS_LIB_ASM_LDO_MANAGEMENT_H__
#ifndef ASSEMBLY
#warning "Header can only be used by assembly sources."
#endif
#include <sof/lib/shim.h>
.macro m_cavs_set_ldo_state state, ax
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
s32i \state, \ax, 0
memw
// wait loop > 300ns (min 100ns required)
movi \ax, 128
1 :
addi \ax, \ax, -1
nop
bnez \ax, 1b
.endm
.macro m_cavs_set_hpldo_state state, ax, ay
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
l32i \ay, \ax, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK)
and \ay, \ax, \ay
or \state, \ay, \state
m_cavs_set_ldo_state \state, \ax
.endm
.macro m_cavs_set_lpldo_state state, ax, ay
movi \ax, (SHIM_BASE + SHIM_LDOCTL)
l32i \ay, \ax, 0
// LP SRAM mask
movi \ax, ~(SHIM_LDOCTL_LPSRAM_MASK)
and \ay, \ax, \ay
or \state, \ay, \state
m_cavs_set_ldo_state \state, \ax
.endm
.macro m_cavs_set_ldo_on_state ax, ay, az
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \ax, \az
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_ON | SHIM_LDOCTL_LPSRAM_LDO_ON)
or \ax, \az, \ax
m_cavs_set_ldo_state \ax, \ay
.endm
.macro m_cavs_set_ldo_off_state ax, ay, az
// wait loop > 300ns (min 100ns required)
movi \ax, 128
1 :
addi \ax, \ax, -1
nop
bnez \ax, 1b
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \az, \ax
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_OFF | SHIM_LDOCTL_LPSRAM_LDO_OFF)
or \ax, \ax, \az
s32i \ax, \ay, 0
l32i \ax, \ay, 0
.endm
.macro m_cavs_set_ldo_bypass_state ax, ay, az
// wait loop > 300ns (min 100ns required)
movi \ax, 128
1 :
addi \ax, \ax, -1
nop
bnez \ax, 1b
movi \ay, (SHIM_BASE + SHIM_LDOCTL)
l32i \az, \ay, 0
movi \ax, ~(SHIM_LDOCTL_HPSRAM_MASK | SHIM_LDOCTL_LPSRAM_MASK)
and \az, \az, \ax
movi \ax, (SHIM_LDOCTL_HPSRAM_LDO_BYPASS | SHIM_LDOCTL_LPSRAM_LDO_BYPASS)
or \ax, \ax, \az
s32i \ax, \ay, 0
l32i \ax, \ay, 0
.endm
#endif /* __CAVS_LIB_ASM_LDO_MANAGEMENT_H__ */

24
src/platform/intel/cavs/include/cavs/lps_ctx.h
View File

@ -1,24 +0,0 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright(c) 2019 Intel Corporation. All rights reserved.
*
* Author: Marcin Maka <marcin.maka@linux.intel.com>
*/
#ifndef __CAVS_LPS_CTX_H__
#define __CAVS_LPS_CTX_H__
#include <xtensa/xtruntime-frames.h>
STRUCT_BEGIN
STRUCT_FIELD(void*, 4, lps_ctx_, vector_level_2)
STRUCT_FIELD(void*, 4, lps_ctx_, vector_level_3)
STRUCT_FIELD(void*, 4, lps_ctx_, vector_level_4)
STRUCT_FIELD(void*, 4, lps_ctx_, vector_level_5)
STRUCT_FIELD(long, 4, lps_ctx_, intenable)
STRUCT_FIELD(long, 4, lps_ctx_, memmap_vecbase_reset)
STRUCT_FIELD(long, 4, lps_ctx_, threadptr)
STRUCT_FIELD(void*, 4, lps_ctx_, task_ctx)
STRUCT_END(lps_ctx)
#endif /*__CAVS_LPS_CTX_H__ */

17
src/platform/intel/cavs/include/cavs/lps_wait.h
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@ -1,17 +0,0 @@
/* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright(c) 2019 Intel Corporation. All rights reserved.
*
* Author: Marcin Maka <marcin.maka@linux.intel.com>
*/
#ifndef __CAVS_LPS_WAIT_H__
#define __CAVS_LPS_WAIT_H__
extern void *lps_pic_restore_vector;
extern void *lps_pic_restore_vector_end;
extern void *lps_pic_restore_vector_literals;
void lps_wait_for_interrupt(int level);
#endif /*__CAVS_LPS_WAIT_H__ */

162
src/platform/intel/cavs/lps_wait.c
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@ -1,162 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
//
// Copyright(c) 2019 Intel Corporation. All rights reserved.
//
// Author: Marcin Maka <marcin.maka@linux.intel.com>
#include <rtos/wait.h>
#include <cavs/lps_ctx.h>
#include <cavs/lps_wait.h>
#include <cavs/mem_window.h>
#include <sof/common.h>
#include <sof/platform.h>
#include <rtos/interrupt.h>
#include <sof/lib/memory.h>
#include <sof/lib/pm_runtime.h>
#include <sof/lib/shim.h>
#include <rtos/task.h>
#include <stdint.h>
#ifdef __ZEPHYR__
/* TODO: declare local copy to avoid naming collisions with Zephyr and SOF */
/* headers until common functions can be separated out */
int memcpy_s(void *dest, size_t dest_size, const void *src, size_t count);
#endif
#define LPSRAM_MAGIC_VALUE 0x13579BDF
#define LPSRAM_HEADER_SIZE 0xc00
struct lpsram_header {
uint32_t alt_reset_vector;
uint32_t adsp_lpsram_magic;
void *lp_restore_vector;
uint32_t reserved;
/* align total size of the structure to the full header size
* with bypass vector area
*/
uint8_t rom_bypass_vectors_reserved[LPSRAM_HEADER_SIZE - 16];
};
#define LPSRAM_HEADER_BYPASS_ADDR (LP_SRAM_BASE - SRAM_ALIAS_OFFSET)
#define LPS_POWER_FLOW_D0_D0I3 1
#define LPS_POWER_FLOW_D0I3_D0 0
#define LPS_BOOT_STACK_SIZE 4096
#define PG_TASK_STACK_SIZE 4096
__aligned(PLATFORM_DCACHE_ALIGN) uint8_t lps_boot_stack[LPS_BOOT_STACK_SIZE];
__aligned(PLATFORM_DCACHE_ALIGN) lps_ctx lps_restore;
static void *pg_task_ctx;
static uint8_t pg_task_stack[PG_TASK_STACK_SIZE];
static void platform_pg_int_handler(void *arg);
static void platform_pg_task(void)
{
struct lpsram_header *lpsram_hdr = (struct lpsram_header *)
LPSRAM_HEADER_BYPASS_ADDR;
size_t vector_size;
size_t offset_to_entry;
int schedule_irq;
_xtos_set_intlevel(5);
xthal_window_spill();
offset_to_entry = (uint32_t)&lps_pic_restore_vector
- (uint32_t)&lps_pic_restore_vector_literals;
vector_size = ALIGN_UP_COMPILE((size_t)&lps_pic_restore_vector_end
- (size_t)&lps_pic_restore_vector_literals, 4);
/* Half of area is available,
* another half is reserved for custom vectors in future (like WHM)
*/
memcpy_s((void *)LPS_RESTORE_VECTOR_ADDR, LPS_RESTORE_VECTOR_SIZE,
&lps_pic_restore_vector_literals, vector_size);
dcache_writeback_invalidate_region((__sparse_force void __sparse_cache *)
LPS_RESTORE_VECTOR_ADDR, vector_size);
/* set magic and vector in LPSRAM */
lpsram_hdr->adsp_lpsram_magic = LPSRAM_MAGIC_VALUE;
lpsram_hdr->lp_restore_vector = (void *)(LPS_RESTORE_VECTOR_ADDR
+ offset_to_entry);
/* re-register to change the direction (arg) */
schedule_irq = interrupt_get_irq(IRQ_NUM_SOFTWARE3, NULL);
interrupt_register(schedule_irq,
platform_pg_int_handler,
(void *)LPS_POWER_FLOW_D0I3_D0);
/* enable all INTs that should turn the dsp on */
arch_interrupt_enable_mask(BIT(PLATFORM_SCHEDULE_IRQ) |
BIT(IRQ_NUM_EXT_LEVEL2) |
BIT(IRQ_NUM_EXT_LEVEL5));
while (1) {
/* flush caches and handle int or pwr off */
xthal_dcache_all_writeback_inv();
arch_wait_for_interrupt(0);
}
}
static void platform_pg_int_handler(void *arg)
{
uint32_t dir = (uint32_t)arg;
if (dir == LPS_POWER_FLOW_D0_D0I3) {
pm_runtime_put(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID);
/* init power flow task */
if (!pg_task_ctx)
task_context_alloc(&pg_task_ctx);
task_context_init(pg_task_ctx, platform_pg_task, NULL, NULL,
PLATFORM_PRIMARY_CORE_ID,
pg_task_stack, sizeof(pg_task_stack));
/* set TCB to power flow task */
task_context_set(pg_task_ctx);
arch_interrupt_disable_mask(0xffffffff);
} else {
pm_runtime_get(PM_RUNTIME_DSP, PLATFORM_PRIMARY_CORE_ID);
/* set TCB to the one stored in platform_power_gate() */
task_context_set(lps_restore.task_ctx);
arch_interrupt_disable_mask(0xffffffff);
#if CONFIG_MEM_WND
platform_memory_windows_init(0);
#endif
arch_interrupt_enable_mask(lps_restore.intenable);
}
}
void lps_wait_for_interrupt(int level)
{
int schedule_irq;
/* store the current state */
lps_restore.intenable = arch_interrupt_get_enabled();
lps_restore.threadptr = cpu_read_threadptr();
lps_restore.task_ctx = (void *)task_context_get();
lps_restore.memmap_vecbase_reset = cpu_read_vecbase();
lps_restore.vector_level_2 = (void *)cpu_read_excsave2();
lps_restore.vector_level_3 = (void *)cpu_read_excsave3();
lps_restore.vector_level_4 = (void *)cpu_read_excsave4();
lps_restore.vector_level_5 = (void *)cpu_read_excsave5();
/* use SW INT handler to do the context switch directly there */
schedule_irq = interrupt_get_irq(IRQ_NUM_SOFTWARE3, NULL);
interrupt_register(schedule_irq,
platform_pg_int_handler,
(void *)LPS_POWER_FLOW_D0_D0I3);
arch_interrupt_disable_mask(0xffffffff);
_xtos_set_intlevel(0);
interrupt_enable(schedule_irq, NULL);
interrupt_set(schedule_irq);
}

3
src/platform/intel/cavs/platform.c
View File

@ -8,9 +8,6 @@
// Janusz Jankowski <janusz.jankowski@linux.intel.com>
#include <cavs/version.h>
#if (CONFIG_CAVS_LPS)
#include <cavs/lps_wait.h>
#endif
#include <sof/common.h>
#include <sof/compiler_info.h>
#include <sof/debug/debug.h>

9
src/platform/tigerlake/include/platform/lib/memory.h
View File

@ -384,17 +384,8 @@
#define LP_SRAM_START LP_SRAM_BASE
#endif
#if (CONFIG_CAVS_LPS)
#define LPS_RESTORE_VECTOR_OFFSET 0x1000
#define LPS_RESTORE_VECTOR_SIZE 0x800
#define LPS_RESTORE_VECTOR_ADDR (LP_SRAM_BASE + LPS_RESTORE_VECTOR_OFFSET)
#define HEAP_LP_BUFFER_BASE (LPS_RESTORE_VECTOR_ADDR + LPS_RESTORE_VECTOR_SIZE)
#define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - LPS_RESTORE_VECTOR_SIZE -\
LPS_RESTORE_VECTOR_OFFSET)
#else
#define HEAP_LP_BUFFER_BASE LP_SRAM_START
#define HEAP_LP_BUFFER_SIZE (LP_SRAM_SIZE - (LP_SRAM_START - LP_SRAM_BASE))
#endif
#define HEAP_LP_BUFFER_BLOCK_SIZE 0x180

4
zephyr/CMakeLists.txt
View File

@ -140,10 +140,6 @@ if (CONFIG_SOC_SERIES_INTEL_CAVS_V25)
${SOF_SRC_PATH}/schedule/zephyr_ll.c
)
zephyr_library_sources_ifdef(CONFIG_CAVS_LPS
${SOF_PLATFORM_PATH}/intel/cavs/lps_wait.c
)
set(PLATFORM "tigerlake")
zephyr_include_directories(${SOF_PLATFORM_PATH}/intel/cavs/include)
endif()