mirror of https://github.com/thesofproject/sof.git
ace: dma: Add temporary dma ops to allow get attributes
The attributes of the dma controllers must be moved to the zephyr. Until then, we will use a own copy of the get_attribute function from the alh and dw_dma drivers. Thanks to this, we can completely disable it building in the configuration. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This commit is contained in:
parent
ac33ac128b
commit
02152c3dcf
|
@ -17,6 +17,71 @@
|
|||
#include <rtos/spinlock.h>
|
||||
#include <zephyr/device.h>
|
||||
|
||||
#define DW_DMA_BUFFER_ALIGNMENT 0x4
|
||||
#define DW_DMA_COPY_ALIGNMENT 0x4
|
||||
#define DW_DMA_BUFFER_PERIOD_COUNT 0x4
|
||||
|
||||
static int dw_dma_get_attribute(struct dma *dma, uint32_t type,
|
||||
uint32_t *value)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (type) {
|
||||
case DMA_ATTR_BUFFER_ALIGNMENT:
|
||||
*value = DW_DMA_BUFFER_ALIGNMENT;
|
||||
break;
|
||||
case DMA_ATTR_COPY_ALIGNMENT:
|
||||
*value = DW_DMA_COPY_ALIGNMENT;
|
||||
break;
|
||||
case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
|
||||
*value = PLATFORM_DCACHE_ALIGN;
|
||||
break;
|
||||
case DMA_ATTR_BUFFER_PERIOD_COUNT:
|
||||
*value = DW_DMA_BUFFER_PERIOD_COUNT;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct dma_ops dw_dma_ops = {
|
||||
.get_attribute = dw_dma_get_attribute,
|
||||
};
|
||||
|
||||
#define HDA_DMA_BUFFER_ALIGNMENT 0x20
|
||||
#define HDA_DMA_COPY_ALIGNMENT 0x20
|
||||
#define HDA_DMA_BUFFER_ADDRESS_ALIGNMENT 0x80
|
||||
#define HDA_DMA_BUFFER_PERIOD_COUNT 2
|
||||
|
||||
static int hda_dma_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
|
||||
{
|
||||
switch (type) {
|
||||
case DMA_ATTR_BUFFER_ALIGNMENT:
|
||||
*value = HDA_DMA_BUFFER_ALIGNMENT;
|
||||
break;
|
||||
case DMA_ATTR_COPY_ALIGNMENT:
|
||||
*value = HDA_DMA_COPY_ALIGNMENT;
|
||||
break;
|
||||
case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
|
||||
*value = HDA_DMA_BUFFER_ADDRESS_ALIGNMENT;
|
||||
break;
|
||||
case DMA_ATTR_BUFFER_PERIOD_COUNT:
|
||||
*value = HDA_DMA_BUFFER_PERIOD_COUNT;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct dma_ops hda_dma_ops = {
|
||||
.get_attribute = hda_dma_get_attribute,
|
||||
};
|
||||
|
||||
SHARED_DATA struct dma dma[] = {
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpgpdma0), okay)
|
||||
{ /* Low Power GP DMAC 0 */
|
||||
|
@ -28,6 +93,7 @@ SHARED_DATA struct dma dma[] = {
|
|||
DMA_DEV_ALH,
|
||||
.channels = 8,
|
||||
},
|
||||
.ops = &dw_dma_ops,
|
||||
.z_dev = DEVICE_DT_GET(DT_NODELABEL(lpgpdma0)),
|
||||
},
|
||||
#endif
|
||||
|
@ -41,6 +107,7 @@ SHARED_DATA struct dma dma[] = {
|
|||
DMA_DEV_ALH,
|
||||
.channels = 8,
|
||||
},
|
||||
.ops = &dw_dma_ops,
|
||||
.z_dev = DEVICE_DT_GET(DT_NODELABEL(lpgpdma1)),
|
||||
},
|
||||
#endif
|
||||
|
@ -52,6 +119,7 @@ SHARED_DATA struct dma dma[] = {
|
|||
.devs = DMA_DEV_HOST,
|
||||
.channels = DT_PROP(DT_NODELABEL(hda_host_in), dma_channels),
|
||||
},
|
||||
.ops = &hda_dma_ops,
|
||||
.z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_host_in)),
|
||||
},
|
||||
#endif
|
||||
|
@ -63,6 +131,7 @@ SHARED_DATA struct dma dma[] = {
|
|||
.devs = DMA_DEV_HOST,
|
||||
.channels = DT_PROP(DT_NODELABEL(hda_host_out), dma_channels),
|
||||
},
|
||||
.ops = &hda_dma_ops,
|
||||
.z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_host_out)),
|
||||
},
|
||||
#endif
|
||||
|
@ -74,6 +143,7 @@ SHARED_DATA struct dma dma[] = {
|
|||
.devs = DMA_DEV_HDA,
|
||||
.channels = DT_PROP(DT_NODELABEL(hda_link_in), dma_channels),
|
||||
},
|
||||
.ops = &hda_dma_ops,
|
||||
.z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_link_in)),
|
||||
},
|
||||
#endif
|
||||
|
@ -85,6 +155,7 @@ SHARED_DATA struct dma dma[] = {
|
|||
.devs = DMA_DEV_HDA,
|
||||
.channels = DT_PROP(DT_NODELABEL(hda_link_out), dma_channels),
|
||||
},
|
||||
.ops = &hda_dma_ops,
|
||||
.z_dev = DEVICE_DT_GET(DT_NODELABEL(hda_link_out)),
|
||||
},
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue