mirror of https://github.com/thesofproject/sof.git
70 lines
1.7 KiB
Plaintext
70 lines
1.7 KiB
Plaintext
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#
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# Topology for generic CHT board with Realtek codecs
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#
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# Include topology builder
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include(`utils.m4')
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include(`dai.m4')
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include(`pipeline.m4')
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include(`ssp.m4')
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# Include TLV library
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include(`common/tlv.m4')
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# Include Token library
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include(`sof/tokens.m4')
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# Include Cherrytrail DSP configuration
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include(`platform/intel/cht.m4')
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#
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# Define the pipelines
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#
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# PCM0 <----> Volume <----> SSP2
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#
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# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s24le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-playback.m4,
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1, 0, 2, s24le,
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48, 1000, 0, 0)
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# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s24le.
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# Schedule 48 frames per 1000us deadline on core 0 with priority 0
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PIPELINE_PCM_ADD(sof/pipe-volume-capture.m4,
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2, 0, 2, s24le,
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48, 1000, 0, 0)
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#
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# DAI configuration
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#
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# SSP port 2 is our only pipeline DAI
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#
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# playback DAI is SSP2 using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-playback.m4,
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1, SSP, 2, SSP2-Codec,
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PIPELINE_SOURCE_1, 2, s24le,
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48, 1000, 0, 0)
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# capture DAI is SSP2 using 2 periods
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# Buffers use s24le format, with 48 frame per 1000us on core 0 with priority 0
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DAI_ADD(sof/pipe-dai-capture.m4,
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2, SSP, 2, SSP2-Codec,
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PIPELINE_SINK_2, 2, s24le,
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48, 1000, 0, 0)
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# PCM Low Latency
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PCM_DUPLEX_ADD(SSP2, 0, PIPELINE_PCM_1, PIPELINE_PCM_2)
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#
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# BE configurations - overrides config in ACPI if present
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#
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DAI_CONFIG(SSP, 2, 0, SSP2-Codec,
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SSP_CONFIG(I2S, SSP_CLOCK(mclk, 19200000, codec_mclk_in),
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SSP_CLOCK(bclk, 2400000, codec_slave),
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SSP_CLOCK(fsync, 48000, codec_slave),
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SSP_TDM(2, 25, 3, 3),
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SSP_CONFIG_DATA(SSP, 2, 24)))
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