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kconfig: allow SOF Kconfig to be included in other projects When the SOF Kconfig is included in other projects, the main menu should not be that of SOF, rather it should be of the project including SOF. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-08-04 06:40:58 +08:00
# SPDX-License-Identifier: BSD-3-Clause
config XT_WAITI_DELAY
bool
default n
help
LX6 Xtensa platforms may require additional delay to flush loads
and stores before entering WAITI.
config HOST_PTABLE
bool
default n
config XT_BOOT_LOADER
bool
default n
config XT_HAVE_RESET_VECTOR_ROM
bool
default n
help
Select if your platform has the reset vector
in ROM.
config XT_IRQ_MAP
bool
default n
config DMA_GW
bool
default n
config MEM_WND
bool
default n
config INTEL_IOMUX
bool
default n
config DMA_HW_LLI
bool
default n
help
Hardware linked list is DMA feature, which allows
to automatically reload the next programmed linked list
item from memory without stopping the transfer. Without
it the transfer stops after every lli read and FW needs
to manually setup the next transfer.
Any platforms with hardware linked list support
should set this.
config DMA_SUSPEND_DRAIN
bool
default n
help
Some platforms cannot just simple disable DMA
channel during the transfer, because it will
hang the whole DMA controller. Instead we can
suspend the channel and drain the FIFO in order
to stop the channel as soon as possible.
Any platforms without the ability to disable
the DMA channel right away should set this.
config DMA_FIFO_PARTITION
bool
default n
help
Some platforms require to manually set DMA
FIFO partitions before starting any transfer.
Any platforms without automatic FIFO partitions
should set this.
config XT_INTERRUPT_LEVEL_1
bool
default n
help
Select if the platform supports any interrupts of level 1.
Disabling this option allows for less memory consumption.
config XT_INTERRUPT_LEVEL_2
bool
default n
help
Select if the platform supports any interrupts of level 2.
Disabling this option allows for less memory consumption.
config XT_INTERRUPT_LEVEL_3
bool
default n
help
Select if the platform supports any interrupts of level 3.
Disabling this option allows for less memory consumption.
config XT_INTERRUPT_LEVEL_4
bool
default n
help
Select if the platform supports any interrupts of level 4.
Disabling this option allows for less memory consumption.
config XT_INTERRUPT_LEVEL_5
bool
default n
help
Select if the platform supports any interrupts of level 5.
Disabling this option allows for less memory consumption.
refactor is_cached() to avoid buggy compiler optimization For imx, is_cached() is implemented based on _memmap_cacheattr_reset. This keeps the attributes for a 512MB region, therefore we have the following address ranges: Address range - hex digit 0 - 1FFFFFFF - 0 20000000 - 3FFFFFFF - 1 40000000 - 5FFFFFFF - 2 60000000 - 7FFFFFFF - 3 80000000 - 9FFFFFFF - 4 A0000000 - BFFFFFFF - 5 C0000000 - DFFFFFFF - 6 E0000000 - FFFFFFFF - 7 While testing on i.MX8ULP we discovered that addresses from (0 – 1FFFFFFF) range where not correctly marked as cacheable, because the compiler is optimizing the code incorrectly. With macros, is_cached(address) expands to (((((uint32_t)(&_memmap_cacheattr_reset_8ulp)) >> \ ((((((uintptr_t)((void *)address) >> 29) & 0x7)) << 2))) \ & 0xF) == 1) When using _memmap_cacheattr_reset_8ulp = 0x22222221 and address = 0x1A801000 is_cached(0x1A801000) should be true, but instead is false. We want to avoid this buggy compiler optimization. So we replaced the macros from cache.h with functions. To make this generic, I created a cache_attr.c file in src/arch/xtensa/drivers/ and a config option - COMPILER_WORKAROUND_CACHE_ATTR, which must be selected if the workaround is needed. Also, we replaced the call to glb_addr_attr() from glb_is_cached() with a function pointer that is initialized in src/arch/xtensa/drivers/cache_attr.c. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2021-08-06 00:24:42 +08:00
config COMPILER_WORKAROUND_CACHE_ATTR
bool
default n
help
Select this to activate use of functions instead of macros
to decide whether an address is cacheable or not.
There is a weird optimization bug with gcc10x and gcc8.1
(with -O2 flags) on IMX platforms. See PR #4605.
kconfig: allow SOF Kconfig to be included in other projects When the SOF Kconfig is included in other projects, the main menu should not be that of SOF, rather it should be of the project including SOF. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-08-04 06:40:58 +08:00
rsource "src/Kconfig"
# See zephyr/modules/Kconfig
if !ZEPHYR_SOF_MODULE
rsource "Kconfig.xtos-build"
endif
sof: replace log calls with zephyr logging api The log context in zephyr is per file or module. To use zephyr logging api, LOG_MODULE_REGISTER is used to register a log context, LOG_MODULE_DECLARE is used to refer to the registered context. For function in header file, LOG_MODULE_DECLARE should be used within that function to avoid context collapse, a condition one source file have multiple context registered or declared. Signed-off-by: Chao Song <chao.song@linux.intel.com>
2022-03-29 15:39:11 +08:00
if ZEPHYR_SOF_MODULE
rsource "Kconfig.zephyr-log"
endif
kconfig: allow SOF Kconfig to be included in other projects When the SOF Kconfig is included in other projects, the main menu should not be that of SOF, rather it should be of the project including SOF. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-08-04 06:40:58 +08:00
menu "Debug"
config DEBUG
bool "Enable debug build"
default n
help
Select for debug build
config GDB_DEBUG
bool "GDB Stub"
default n
help
Select for GDB debugging
config DEBUG_MEMORY_USAGE_SCAN
bool "Memory usage scan"
default y
help
It enables memory usage scan at demand in runtime.
This feature does not affect standard memory operations,
especially allocation and deallocation.
config DEBUG_LOCKS
bool "Spinlock debug"
default n
help
It adds additional information to the spinlocks about
the current user of the lock. Also executes panic
on deadlock.
config DEBUG_LOCKS_VERBOSE
bool "Spinlock verbose debug"
depends on DEBUG_LOCKS
default n
help
In addition to DEBUG_LOCKS it also adds spinlock traces
every time the lock is acquired.
config DEBUG_IPC_COUNTERS
bool "IPC counters"
depends on CAVS
depends on DEBUG
default n
help
Select for enabling tracing IPC counter in SRAM_REG mailbox
ll_schedule: Update DSP load tracker to provide per task numbers Calculates average and records the maximum execution cycles taken by each execution round and prints the results out once every 1024 round, e.g. roughly once per second with a typical 1ms tick configuration. The output is mimicked from the Zephyr side scheduler output. There is a Kconfig menu option under debug menu to disable this feature. Currently the default is on. Signed-off-by: Jyri Sarha <jyri.sarha@intel.com>
2022-03-17 23:23:41 +08:00
config SCHEDULE_LOG_CYCLE_STATISTICS
bool "Log cycles per tick statistics for each task separately"
default y
help
Log DSP cycle usage statistics about once per second (1ms *
1024) for each task separately. The printed data is task's
meta information, average number of cycles/tick, and maximum
number of cycles/tick during the previous 1024 tick period.
kconfig: allow SOF Kconfig to be included in other projects When the SOF Kconfig is included in other projects, the main menu should not be that of SOF, rather it should be of the project including SOF. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-08-04 06:40:58 +08:00
config PERFORMANCE_COUNTERS
bool "Performance counters"
default n
help
Enables tracing of simple performance measurements.
A basic use case is to measure number of platform & cpu clock ticks
passed between two checkpoints (init() and stamp()), for example
total time spent on running low latency scheduler tasks.
Platforms that gate cpu clock in wait-for-interrupt calls may also
use the stamp() macro periodically to find out how long the cpu
was in active/sleep state between the calls and estimate the cpu load.
perf_cnt: add the tracing of window-based average calculation The average number of cpu cycles/ticks spent could be provided per 1024 scheduled tasks by the performance counter. It would be more accurate for MCPS measurement than the peak number. Even so, the tracing macro will log both of them to provide more insights. This is enabled by CONFIG_PERFORMANCE_COUNTERS_RUN_AVERAGE, which depends on CONFIG_PERFORMANCE_COUNTERS. Signed-off-by: Pin-chih Lin <johnylin@google.com>
2022-04-13 00:38:32 +08:00
config PERFORMANCE_COUNTERS_RUN_AVERAGE
bool "Performance counters run average"
depends on PERFORMANCE_COUNTERS
default n
help
Enables tracing of performance measurements with window-based average
calculations. In addition to the usage of stamp(), the performance
counter will compute the average number of cpu cycles/ticks spent
within the window size of 1024 scheduled tasks and log it out via
tracings.
kconfig: allow SOF Kconfig to be included in other projects When the SOF Kconfig is included in other projects, the main menu should not be that of SOF, rather it should be of the project including SOF. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-08-04 06:40:58 +08:00
config DSP_RESIDENCY_COUNTERS
bool "DSP residency counters"
default n
help
Enables simple DSP residency counters in SRAM_REG mailbox.
R0, R1, R2 are abstract states which can be used differently
based on platform implementation.
if !ZEPHYR_SOF_MODULE
rsource "Kconfig.xtos-dbg"
endif
endmenu