2017-07-06 23:41:09 +08:00
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#
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# Cherrytrail differentiation for pipelines and components
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#
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2018-03-05 21:38:12 +08:00
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include(`memory.m4')
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dnl Memory capabilities for diferent buffer types on Cherrytrail
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define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE))
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define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE))
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define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE))
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define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE))
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2017-07-06 23:41:09 +08:00
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# Low Latency PCM Configuration
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2018-03-06 05:58:32 +08:00
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W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"'))
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2017-07-06 23:41:09 +08:00
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2018-03-06 05:58:33 +08:00
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W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens)
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2017-07-06 23:41:09 +08:00
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# Media PCM Configuration
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2018-03-06 05:58:32 +08:00
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W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "100000"'))
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2017-07-06 23:41:09 +08:00
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2018-03-06 05:58:33 +08:00
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W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens)
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2017-07-06 23:41:09 +08:00
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# Tone Signal Generator Configuration
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2018-03-06 05:58:32 +08:00
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W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "200000"'))
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2017-07-06 23:41:09 +08:00
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2018-03-06 05:58:33 +08:00
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W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens)
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2017-07-06 23:41:09 +08:00
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2017-08-09 21:50:57 +08:00
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# DAI schedule Configuration - scheduled by IRQ
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2018-03-06 05:58:32 +08:00
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W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "5000"'))
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2017-08-09 21:50:57 +08:00
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2018-03-06 05:58:33 +08:00
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W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens)
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2019-01-11 09:52:14 +08:00
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VIRTUAL_WIDGET(codec_out0, output, 1)
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VIRTUAL_WIDGET(codec_out1, output, 2)
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VIRTUAL_WIDGET(codec_in0, input, 3)
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VIRTUAL_WIDGET(codec_in1, input, 4)
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