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sof/tools/topology/topology1/sof-icl-dmic-4ch.m4

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topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
#
# Topology for ICL Lake with direct attach digital microphones array
#
# Include topology builder
include(`utils.m4')
include(`dai.m4')
include(`pipeline.m4')
# Include TLV library
include(`common/tlv.m4')
# Include Token library
include(`sof/tokens.m4')
topology: add platform sku files to config platform settings icl, cml whl are sharing some toplogy files. Create platform specific files including DSP configuration, SSP setting and DMIC to simplify platform settings. Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
2020-03-03 09:45:42 +08:00
# Include IceLake DSP configuration
include(`platform/intel/icl.m4')
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
#
# Define the pipelines
#
# PCM6 <---- volume <----- DMIC01 (dmic0 capture)
#
topology: revert all cAVS pipelines to 2 periods Reverts all previosly changed cAVS pipelines from 3 to 2 periods. Now we have separate buffers for DMA, so there is no need to make DAI buffers consist of 3 periods. DMA will take care of any internal hardware requirements. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-22 15:09:58 +08:00
dnl PIPELINE_PCM_ADD(pipeline,
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
dnl pipe id, pcm, max channels, format,
topology: enable pcm range and pipeline rate and remove frame count Enable setting pcm min and max rate from top level m4 pipeline macro. This way it is possible to configure the whole pipeline to correct samplerate range in 1 file. Previously you needed to modify the pipeline macros where the rate was hardcoded. As the frame count is calculated from pcm/dai rate and scheduling time the frame count is obsolete. Introduce pipeline rate parameter to help configuring components with fixed output rate. We can't deduce this from pcm range since for example src might accept bigger max rate than the following dai. Even though the parameter is named "pipeline rate" it essentially means the "final" output rate to which this pipeline is connected to (dai or other pipeline). In capture pipelines it means the originating fixed dai rate. Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-01-03 20:11:21 +08:00
dnl period, priority, core,
topology: revert all cAVS pipelines to 2 periods Reverts all previosly changed cAVS pipelines from 3 to 2 periods. Now we have separate buffers for DMA, so there is no need to make DAI buffers consist of 3 periods. DMA will take care of any internal hardware requirements. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-22 15:09:58 +08:00
dnl pcm_min_rate, pcm_max_rate, pipeline_rate,
dnl time_domain, sched_comp)
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
# Passthrough capture pipeline 1 on PCM 1 using max 4 channels.
topology1: correct misleading comments for priority/core Comments for calls to PIPELINE_PCM_ADD and DAI_ADD describe parameters in the same order they are passed to the macros. The only exception is order of "priority" and "core", and this can be very misleading. In most cases the actual current values for the two parameters are 0, making it even easier to make a mistake when modifying them. Fix the order in the comments to match the actual order in which the parameters should be passed to PIPELINE_PCM_ADD and DAI_ADD. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2021-09-15 20:48:14 +08:00
# 1000us deadline with priority 0 on core 0
topology: revert all cAVS pipelines to 2 periods Reverts all previosly changed cAVS pipelines from 3 to 2 periods. Now we have separate buffers for DMA, so there is no need to make DAI buffers consist of 3 periods. DMA will take care of any internal hardware requirements. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-22 15:09:58 +08:00
PIPELINE_PCM_ADD(sof/pipe-passthrough-capture.m4,
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
1, 1, 4, s32le,
topology: revert all cAVS pipelines to 2 periods Reverts all previosly changed cAVS pipelines from 3 to 2 periods. Now we have separate buffers for DMA, so there is no need to make DAI buffers consist of 3 periods. DMA will take care of any internal hardware requirements. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-22 15:09:58 +08:00
1000, 0, 0,
topology: enable pcm range and pipeline rate and remove frame count Enable setting pcm min and max rate from top level m4 pipeline macro. This way it is possible to configure the whole pipeline to correct samplerate range in 1 file. Previously you needed to modify the pipeline macros where the rate was hardcoded. As the frame count is calculated from pcm/dai rate and scheduling time the frame count is obsolete. Introduce pipeline rate parameter to help configuring components with fixed output rate. We can't deduce this from pcm range since for example src might accept bigger max rate than the following dai. Even though the parameter is named "pipeline rate" it essentially means the "final" output rate to which this pipeline is connected to (dai or other pipeline). In capture pipelines it means the originating fixed dai rate. Signed-off-by: Jaska Uimonen <jaska.uimonen@intel.com>
2019-01-03 20:11:21 +08:00
48000, 48000, 48000)
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
#
# DAIs configuration
#
dnl DAI_ADD(pipeline,
dnl pipe id, dai type, dai_index, dai_be,
dnl buffer, periods, format,
topology: icl: use 3 periods for SSP, DMIC and ALH DAIs Changes number of SSP, DMIC and ALH DAI periods from 2 to 3. This way we can support both timer and new single DMA channel scheduling. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-09-20 17:09:07 +08:00
dnl deadline, priority, core, time_domain)
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
topology: revert all cAVS pipelines to 2 periods Reverts all previosly changed cAVS pipelines from 3 to 2 periods. Now we have separate buffers for DMA, so there is no need to make DAI buffers consist of 3 periods. DMA will take care of any internal hardware requirements. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-22 15:09:58 +08:00
# capture DAI is DMIC 0 using 2 periods
topology1: correct misleading comments for priority/core Comments for calls to PIPELINE_PCM_ADD and DAI_ADD describe parameters in the same order they are passed to the macros. The only exception is order of "priority" and "core", and this can be very misleading. In most cases the actual current values for the two parameters are 0, making it even easier to make a mistake when modifying them. Fix the order in the comments to match the actual order in which the parameters should be passed to PIPELINE_PCM_ADD and DAI_ADD. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
2021-09-15 20:48:14 +08:00
# Buffers use s32le format, 1000us deadline with priority 0 on core 0
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
DAI_ADD(sof/pipe-dai-capture.m4,
1, DMIC, 0, dmic01,
topology: revert all cAVS pipelines to 2 periods Reverts all previosly changed cAVS pipelines from 3 to 2 periods. Now we have separate buffers for DMA, so there is no need to make DAI buffers consist of 3 periods. DMA will take care of any internal hardware requirements. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-22 15:09:58 +08:00
PIPELINE_SINK_1, 2, s32le,
topology: cavs: switch all pipelines to timer scheduling Switches all pipelines for cAVS platforms to timer scheduling. This way we limit the number of interrupt levels processed in the system. Timer, IPC and IDC are already on level 2 and DMAs are on level 5. Signed-off-by: Tomasz Lauda <tomasz.lauda@linux.intel.com>
2019-10-15 19:40:26 +08:00
1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER)
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture)
dnl PCM_CAPTURE_ADD(name, pipeline, capture)
topology: fix DMIC device names DMIC01 is just useless for a user. After multiple rounds of discussion, we agreed to remove numbers (which could be understood as a mic position) or a frequency (which is misleading since it can be updated to e.g. 96kHz by topology), so by default the DMIC interface is called just that... Conversely, we add a clear 16kHz qualifier for the low-frequency path. While in theory the frequency can be changed with modifications of the FIR filter, applications do need 16kHz support. Also make sure we only use 'DMIC' for 'PCH-attached DMICs'. For RT715-based solutions, the microphones can be analog, so use more generic 'Microphones' description. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2019-12-10 00:19:56 +08:00
PCM_CAPTURE_ADD(DMIC, 1, PIPELINE_PCM_1)
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
#
# BE configurations - overrides config in ACPI if present
#
dnl DAI_CONFIG(type, dai_index, link_id, name, ssp_config/dmic_config)
DAI_CONFIG(DMIC, 0, 1, dmic01,
Topology: Change minimum bus clock to 2.4 MHz for 48 kHz DMIC DAI The driver configures a lowest feasible bus clock to save power. Since the 48 kHz and 16 kHz DMIC DAI can now be instantiated in the runtime there is possibility that the min. 500 kHz clock allowed could be too low for a new 48 kHz capture when existing 16 kHz capture is running. The topologies those define a 48 kHz DMIC DAI need to increase the min. clock to a sufficient rate. This patch changes every 500 kHz value to 2.4 MHz. This change does not change the external microphone clock in any platform. The lower than 2.4 MHz clock rates never happened in previous version to due to the 48 kHz DAI request in these topologies. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2020-11-07 00:11:07 +08:00
DMIC_CONFIG(1, 2400000, 4800000, 40, 60, 48000,
Topology: Add SOF_TKN_INTEL_DMIC_UNMUTE_RAMP_TIME_MS token This patch adds to all DMIC related topologies the new token SOF_TKN_INTEL_DMIC_UNMUTE_RAMP_TIME_MS. The value is set to 400 to correspond to 400 milliseconds long unmute ramp time. The topology defined unmute will override the firmware internal hard coded value if it is set in topology. Signed-off-by: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
2019-06-03 22:35:13 +08:00
DMIC_WORD_LENGTH(s32le), 400, DMIC, 0,
topology: add 4-ch dmic topology for ICL Signed-off-by: Zhang Keqiao <keqiao.zhang@linux.intel.com>
2018-11-21 16:06:21 +08:00
PDM_CONFIG(DMIC, 0, FOUR_CH_PDM0_PDM1)))