363 lines
18 KiB
Python
363 lines
18 KiB
Python
## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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sys.dont_write_bytecode = True
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sys.path.append (os.path.join('..', '..'))
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from BuildLoader import BaseBoard, STITCH_OPS
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from BuildLoader import IPP_CRYPTO_OPTIMIZATION_MASK, IPP_CRYPTO_ALG_MASK, HASH_TYPE_VALUE, HASH_USAGE
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class Board(BaseBoard):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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EXECUTE_IN_PLACE = 0
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FREE_TEMP_RAM_TOP = 0x70000
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self.VERINFO_IMAGE_ID = 'SB_QEMU '
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 1
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self.VERINFO_SVN = 1
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self.VERINFO_BUILD_DATE = '05/03/2021'
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self.BOARD_NAME = 'qemu'
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self.BOARD_PKG_NAME = 'QemuBoardPkg'
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self.SILICON_PKG_NAME = 'QemuSocPkg'
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#
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# By default,
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# _PCI_ENUM_DOWNGRADE_IO32 : 1
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# _PCI_ENUM_DOWNGRADE_MEM64 : 1
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# _PCI_ENUM_DOWNGRADE_PMEM64: 1
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# _PCI_ENUM_BUS_SCAN_TYPE : 0 (0: list, 1: range)
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#
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#self._PCI_ENUM_DOWNGRADE_IO32 = 0
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#self._PCI_ENUM_DOWNGRADE_MEM64 = 0
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#self._PCI_ENUM_DOWNGRADE_PMEM64 = 0
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#self._PCI_ENUM_BUS_SCAN_TYPE = 1
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self._PCI_ENUM_BUS_SCAN_ITEMS = '0,10,0x35,128,0xff'
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self.PCI_IO_BASE = 0x00002000
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self.PCI_MEM32_BASE = 0x80000000
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self.USB_KB_POLLING_TIMEOUT = 10
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self.HAVE_VERIFIED_BOOT = 1
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self.HAVE_VBT_BIN = 1
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self.ENABLE_SPLASH = 1
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self.ENABLE_FRAMEBUFFER_INIT = 1
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self.ENABLE_FWU = 1
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self.ENABLE_GRUB_CONFIG = 1
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self.ENABLE_LINUX_PAYLOAD = 1
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self.ENABLE_CRYPTO_SHA_OPT = 0
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self.ENABLE_SMBIOS = 1
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# 0: Disable 1: Enable 2: Auto (disable for UEFI payload, enable for others)
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self.ENABLE_SMM_REBASE = 2
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self.ENABLE_SMBIOS = 1
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self.ENABLE_SBL_SETUP = 0
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self.CPU_MAX_LOGICAL_PROCESSOR_NUMBER = 255
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# RSA2048 or RSA3072
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self._RSA_SIGN_TYPE = 'RSA3072'
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# 'SHA2_256' or 'SHA2_384'
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self._SIGN_HASH = 'SHA2_384'
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# 0x01 for SHA2_256 or 0x02 for SHA2_384
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self.SIGN_HASH_TYPE = HASH_TYPE_VALUE[self._SIGN_HASH]
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# 0x0010 for SM3_256 | 0x0008 for SHA2_512 | 0x0004 for SHA2_384 | 0x0002 for SHA2_256 | 0x0001 for SHA1
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self.IPP_HASH_LIB_SUPPORTED_MASK = IPP_CRYPTO_ALG_MASK[self._SIGN_HASH]
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self._MASTER_PRIVATE_KEY = 'KEY_ID_MASTER' + '_' + self._RSA_SIGN_TYPE
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self._CFGDATA_PRIVATE_KEY = 'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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self._CONTAINER_PRIVATE_KEY = 'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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# To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
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# self.ENABLE_SOURCE_DEBUG = 1
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# For test purpose
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# self.SKIP_STAGE1A_SOURCE_DEBUG = 1
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# BIT0:Serial BIT1:USB KB
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# Support serial port input console by default
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self.CONSOLE_IN_DEVICE_MASK = 0x00000001
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# BIT0:Serial BIT1:GFX
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self.CONSOLE_OUT_DEVICE_MASK = 0x00000001
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# Let Stage1A verifies Stage1B
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self.VERIFIED_BOOT_STAGE_1B = 0x1
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self.STAGE1B_XIP = 0
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self.STAGE1A_SIZE = 0x00010000
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if self.NO_OPT_MODE:
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self.STAGE1A_SIZE += 0x1000
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self.STAGE1B_SIZE = 0x00030000
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self.STAGE2_SIZE = 0x00018000
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self.TEST_SIZE = 0x00001000
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self.SIIPFW_SIZE = 0x00010000
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self.EPAYLOAD_SIZE = 0x0020D000
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self.PAYLOAD_SIZE = 0x00020000
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self.CFGDATA_SIZE = 0x00001000
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self.KEYHASH_SIZE = 0x00001000
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self.VARIABLE_SIZE = 0x00002000
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self.SBLRSVD_SIZE = 0x00001000
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self.FWUPDATE_SIZE = 0x00018000 if self.ENABLE_FWU else 0
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self.SETUP_SIZE = 0x00020000 if self.ENABLE_SBL_SETUP else 0
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self._REDUNDANT_LAYOUT = 1
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if not self._REDUNDANT_LAYOUT:
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self.TOP_SWAP_SIZE = 0x000000
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self.REDUNDANT_SIZE = 0x000000
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self.NON_VOLATILE_SIZE = 0x000000
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self.NON_REDUNDANT_SIZE = 0x400000
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else:
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self.TOP_SWAP_SIZE = 0x010000
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if self.NO_OPT_MODE:
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self.TOP_SWAP_SIZE = 0x020000
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self.REDUNDANT_SIZE = 0x080000
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self.NON_VOLATILE_SIZE = 0x001000
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self.NON_REDUNDANT_SIZE = 0x2DF000
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self.SLIMBOOTLOADER_SIZE = (self.TOP_SWAP_SIZE + self.REDUNDANT_SIZE) * 2 + \
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self.NON_REDUNDANT_SIZE + self.NON_VOLATILE_SIZE
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self.STAGE1A_XIP = EXECUTE_IN_PLACE
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if not self.STAGE1A_XIP:
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# For Stage1A, STAGE1_FD_BASE is always located at 4GB - STAGE1_FD_SIZE
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# And execution will start from there. If STAGE1A_XIP is 0, Stage1A
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# will relocate itself to STAGE1A_LOAD_BASE to continue execution
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self.STAGE1A_LOAD_BASE = FREE_TEMP_RAM_TOP
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self.STAGE1B_XIP = EXECUTE_IN_PLACE
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if not self.STAGE1B_XIP:
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# For Stage1B, it can be compressed if STAGE1B_XIP is 0
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# If so, STAGE1B_FD_BASE/STAGE1B_FD_SIZE need to be defined
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self.STAGE1B_FD_SIZE = 0x30000
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if self.NO_OPT_MODE:
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self.STAGE1B_FD_SIZE += 0xE000
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self.STAGE1B_FD_BASE = FREE_TEMP_RAM_TOP - self.STAGE1B_FD_SIZE
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# For Stage2, it is always compressed.
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# if STAGE2_LOAD_HIGH is 1, STAGE2_FD_BASE will be ignored
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self.STAGE2_FD_BASE = 0x01000000
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self.STAGE2_FD_SIZE = 0x00060000
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if self.NO_OPT_MODE:
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if self.FSPDEBUG_MODE == 1:
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self.STAGE2_SIZE += 0x8000
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else:
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self.STAGE2_SIZE += 0x2000
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self.PAYLOAD_SIZE += 0xA000
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self.OS_LOADER_FD_SIZE += 0x23000
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self.FWUPDATE_SIZE += 0x8000
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self.OS_LOADER_FD_NUMBLK = self.OS_LOADER_FD_SIZE // self.FLASH_BLOCK_SIZE
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self.STAGE1_STACK_SIZE = 0x00002000
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self.STAGE1_DATA_SIZE = 0x0000E000
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self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
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# Add following to force to use a specific platform ID
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# By default it uses auto-detection.
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#self._PLATFORM_ID = 1
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self._CFGDATA_INT_FILE = []
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self._CFGDATA_EXT_FILE = ['CfgDataExt_Brd1.dlt', 'CfgDataExt_Brd31.dlt', 'CfgDataExt_QSP.dlt']
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# If mulitple VBT table support is required, list them as:
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# {VbtImageId1 : VbtFileName1, VbtImageId2 : VbtFileName2, ...}
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# VbtImageId is ID to identify a VBT image. It is a UINT32 number to match
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# the ImageId field in the VBT container.
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# VbtFileName is the VBT file name. It needs to be located under platform
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# VbtBin folder.
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self._MULTI_VBT_FILE = {1:'Vbt800x600.dat', 2:'Vbt1024x768.dat'}
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def GetPlatformToolchainVersions(self):
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version_dict = {
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'iasl' : '20160318',
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}
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return version_dict
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def PlatformBuildHook (self, build, phase):
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if phase == 'post-build:before':
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# Create PTEST.bin
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bins = bytearray (b'12345678')
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file = build._fv_dir + '/PTEST.bin'
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with open(file, 'wb') as fd:
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fd.write(bins)
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def GetPlatformDsc (self):
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dsc = {}
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dsc['LibraryClasses.%s' % self.BUILD_ARCH] = [
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'LoaderLib|Platform/CommonBoardPkg/Library/LoaderLib/LoaderLib.inf',
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'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
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'GpioLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioLib/GpioLib.inf',
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'SpiFlashLib|Silicon/$(SILICON_PKG_NAME)/Library/SpiFlashLib/SpiFlashLib.inf',
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'GraphicsInitLib|Silicon/CommonSocPkg/Library/EmuGfxInitLib/EmuGfxInitLib.inf',
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'BootGuardLib|Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
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]
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dsc['PcdsFeatureFlag.%s' % self.BUILD_ARCH] = [
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'gPlatformCommonLibTokenSpaceGuid.PcdMultiUsbBootDeviceEnabled | TRUE'
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]
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return dsc
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def GetKeyHashList (self):
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# Define a set of new key used for different purposes
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# The key is either key id or public key PEM format or private key PEM format
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pub_key_list = [
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(
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# Key for verifying Config data blob
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HASH_USAGE['PUBKEY_CFG_DATA'],
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'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying firmware update
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HASH_USAGE['PUBKEY_FWU'],
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'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying container header
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HASH_USAGE['PUBKEY_CONT_DEF'],
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'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# key for veryfying OS image.
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HASH_USAGE['PUBKEY_OS'],
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'KEY_ID_OS1_PUBLIC' + '_' + self._RSA_SIGN_TYPE
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),
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]
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return pub_key_list
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def GetContainerList (self):
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container_list = []
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container_list_auth_type = self._RSA_SIGN_TYPE + '_'+ self._SIGNING_SCHEME[4:] + '_' + self._SIGN_HASH
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container_list.append ([
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# Name | Image File | CompressAlg | AuthType | Key File | Region Align | Region Size | Svn Info
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# ==================================================================================================================================================================
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('IPFW', 'SIIPFW.bin', '', container_list_auth_type, 'KEY_ID_CONTAINER'+'_'+self._RSA_SIGN_TYPE, 0, 0, 0), # Container Header
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('TST1', '', 'Dummy', '', '', 0, 0x2000, 0), # Component 1
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('TST2', '', 'Lz4', '', '', 0, 0x3000, 0), # Component 2
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('TST3', '', 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, 0x3000, 0), # Component 3
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('TST4', '', 'Lzma', 'SHA2_384', '', 0, 0x3000, 0), # Component 4
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('TST5', '', 'Dummy', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, 0x3000, 0), # Component 5
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('TST6', '', '', '', '', 0, 0x1000, 0), # Component 6
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])
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if self.ENABLE_SBL_SETUP:
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def_auth = container_list_auth_type
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cont_key = 'KEY_ID_CONTAINER'+'_'+self._RSA_SIGN_TYPE
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mpy_efi = 'PayloadPkg/PayloadBins/MicroPython.efi'
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if not os.path.isfile(mpy_efi):
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raise Exception ("MicroPython.efi is required under 'PayloadPkg/PayloadBins', please build MicroPython payload module separately !")
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mpy_path = '../../../' + mpy_efi
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sbl_setup = '../../../BootloaderCorePkg/Tools/SblSetup.py'
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container_list.append ([
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# Name | Image File | CompressAlg | AuthType | Key File | Region Align | Region Size | Svn Info
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# ==================================================================================================================================================================
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('SETP', 'SETP.bin', '', def_auth, cont_key, 0, 0, 0), # Container Header
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('MPYM', mpy_path, 'Lzma', 'SHA2_384', '', 0, 0x12000, 0), # Component 1
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('STPY', sbl_setup, 'Lz4', 'SHA2_384', '', 0, 0x06000, 0), # Component 2
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('CFGJ', 'CfgDataDef.json', 'Lzma', 'SHA2_384', '', 0, 0x06000, 0), # Component 3
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('CFGD', '', 'Dummy', '', '', 0, 0x01000, 0), # Component 4
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])
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return container_list
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def GetOutputImages (self):
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# define extra images that will be copied to output folder
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img_list = ['CfgDataStitch.py',
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'CfgDataDef.yaml']
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return img_list
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def GetImageLayout (self):
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compress = '' if self.STAGE1B_XIP else 'Lz4'
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fwu_mode = STITCH_OPS.MODE_FILE_PAD if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
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setup_mode = STITCH_OPS.MODE_FILE_PAD if self.ENABLE_SBL_SETUP else STITCH_OPS.MODE_FILE_IGNOR
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img_list = []
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# output files need to have unique base name (excluding file extension)
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# output files ends with 'rom' extension will be copied over for final stitching
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if self.REDUNDANT_SIZE == 0:
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img_list.extend ([
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('SlimBootloader.bin', [
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('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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('PAYLOAD.bin' , 'Lzma' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('EPAYLOAD.bin' , '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1B.fd' , compress , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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])
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else:
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img_list.extend ([
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('NON_VOLATILE.bin', [
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('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('NON_REDUNDANT.bin', [
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('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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('PAYLOAD.bin' , 'Lzma' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('EPAYLOAD.bin' , '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('SIIPFW.bin' , '' , self.SIIPFW_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('PTEST.bin' , '' , self.TEST_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('SETP.bin' , '' , self.SETUP_SIZE, setup_mode, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('REDUNDANT_A.bin', [
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('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1B_A.fd' , compress , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, fwu_mode, STITCH_OPS.MODE_POS_TAIL),
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('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('REDUNDANT_B.bin', [
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('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1B_B.fd' , compress , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, fwu_mode, STITCH_OPS.MODE_POS_TAIL),
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('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('TOP_SWAP_A.bin', [
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('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('TOP_SWAP_B.bin', [
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('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('SlimBootloader.bin', [
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('NON_VOLATILE.bin' , '' , self.NON_VOLATILE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('NON_REDUNDANT.bin' , '' , self.NON_REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('REDUNDANT_B.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('REDUNDANT_A.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('TOP_SWAP_B.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('TOP_SWAP_A.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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]
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),
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])
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return img_list
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