309 lines
9.9 KiB
Plaintext
309 lines
9.9 KiB
Plaintext
/** @file
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ACPI DSDT table
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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Scope(\_SB) {
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Name(PD00, Package(){
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// If the setting changed in PCH PxRcConfig policy, platform should also update static assignment here.
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// PCI Bridge
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// D31: cAVS, SMBus, GbE, Nothpeak
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Package(){0x001FFFFF, 0, 0, 11 },
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Package(){0x001FFFFF, 1, 0, 10 },
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Package(){0x001FFFFF, 2, 0, 11 },
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Package(){0x001FFFFF, 3, 0, 11 },
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// D30: SerialIo and SCS - can't use PIC
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// D29: PCI Express Port 9-16
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Package(){0x001DFFFF, 0, 0, 11 },
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Package(){0x001DFFFF, 1, 0, 10 },
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Package(){0x001DFFFF, 2, 0, 11 },
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Package(){0x001DFFFF, 3, 0, 11 },
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// D28: PCI Express Port 1-8
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Package(){0x001CFFFF, 0, 0, 11 },
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Package(){0x001CFFFF, 1, 0, 10 },
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Package(){0x001CFFFF, 2, 0, 11 },
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Package(){0x001CFFFF, 3, 0, 11 },
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// D27: PCI Express Port 17-20
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Package(){0x001BFFFF, 0, 0, 11 },
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Package(){0x001BFFFF, 1, 0, 10 },
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Package(){0x001BFFFF, 2, 0, 11 },
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Package(){0x001BFFFF, 3, 0, 11 },
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// D25: SerialIo - can't use PIC
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// D23: SATA controller
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Package(){0x0017FFFF, 0, 0, 11 },
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// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
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Package(){0x0016FFFF, 0, 0, 11 },
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Package(){0x0016FFFF, 1, 0, 10 },
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Package(){0x0016FFFF, 2, 0, 11 },
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Package(){0x0016FFFF, 3, 0, 11 },
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// D21: SerialIo - can't use PIC
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// SKL: D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
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// CNL: D20: xHCI, OTG, CNVi WiFi, SDcard
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Package(){0x0014FFFF, 0, 0, 11 },
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Package(){0x0014FFFF, 1, 0, 10 },
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Package(){0x0014FFFF, 2, 0, 11 },
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Package(){0x0014FFFF, 3, 0, 11 },
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// D19: Integrated Sensor Hub - can't use PIC
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// D18: Thermal, UFS, SerialIo SPI2 - can't use PIC
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Package(){0x0012FFFF, 0, 0, 11 },
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Package(){0x0012FFFF, 1, 0, 10 },
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Package(){0x0012FFFF, 2, 0, 11 },
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Package(){0x0012FFFF, 3, 0, 11 },
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// Host Bridge
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// P.E.G. Root Port D1F0
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Package(){0x0001FFFF, 0, 0, 11 },
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Package(){0x0001FFFF, 1, 0, 10 },
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Package(){0x0001FFFF, 2, 0, 11 },
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Package(){0x0001FFFF, 3, 0, 11 },
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// P.E.G. Root Port D1F1
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// P.E.G. Root Port D1F2
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// SA IGFX Device
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Package(){0x0002FFFF, 0, 0, 11 },
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// SA Thermal Device
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Package(){0x0004FFFF, 0, 0, 11 },
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// SA IPU Device
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Package(){0x0005FFFF, 0, 0, 11 },
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// SA GNA Device
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Package(){0x0008FFFF, 0, 0, 11 },
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})
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Name(AR00, Package(){
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// PCI Bridge
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// D31: cAVS, SMBus, GbE, Nothpeak
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Package(){0x001FFFFF, 0, 0, 16 },
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Package(){0x001FFFFF, 1, 0, 17 },
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Package(){0x001FFFFF, 2, 0, 18 },
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Package(){0x001FFFFF, 3, 0, 19 },
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// D30: SerialIo and SCS
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Package(){0x001EFFFF, 0, 0, 20 },
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Package(){0x001EFFFF, 1, 0, 21 },
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Package(){0x001EFFFF, 2, 0, 22 },
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Package(){0x001EFFFF, 3, 0, 23 },
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// D29: PCI Express Port 9-16
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Package(){0x001DFFFF, 0, 0, 16 },
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Package(){0x001DFFFF, 1, 0, 17 },
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Package(){0x001DFFFF, 2, 0, 18 },
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Package(){0x001DFFFF, 3, 0, 19 },
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// D28: PCI Express Port 1-8
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Package(){0x001CFFFF, 0, 0, 16 },
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Package(){0x001CFFFF, 1, 0, 17 },
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Package(){0x001CFFFF, 2, 0, 18 },
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Package(){0x001CFFFF, 3, 0, 19 },
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// D27: PCI Express Port 17-20
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Package(){0x001BFFFF, 0, 0, 16 },
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Package(){0x001BFFFF, 1, 0, 17 },
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Package(){0x001BFFFF, 2, 0, 18 },
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Package(){0x001BFFFF, 3, 0, 19 },
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// D26: eMMC
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Package(){0x001AFFFF, 0, 0, 16 },
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Package(){0x001AFFFF, 1, 0, 17 },
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Package(){0x001AFFFF, 2, 0, 18 },
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Package(){0x001AFFFF, 3, 0, 19 },
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// D25: SerialIo
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Package(){0x0019FFFF, 0, 0, 32 },
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Package(){0x0019FFFF, 1, 0, 33 },
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Package(){0x0019FFFF, 2, 0, 34 },
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// D23: SATA controller
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Package(){0x0017FFFF, 0, 0, 16 },
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// D22: CSME (HECI, IDE-R, Keyboard and Text redirection
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Package(){0x0016FFFF, 0, 0, 16 },
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Package(){0x0016FFFF, 1, 0, 17 },
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Package(){0x0016FFFF, 2, 0, 18 },
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Package(){0x0016FFFF, 3, 0, 19 },
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// D21: SerialIo
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Package(){0x0015FFFF, 0, 0, 16 },
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Package(){0x0015FFFF, 1, 0, 17 },
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Package(){0x0015FFFF, 2, 0, 18 },
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Package(){0x0015FFFF, 3, 0, 19 },
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// SKL: D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
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// CNL: D20: xHCI, OTG, CNVi WiFi, SDcard
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Package(){0x0014FFFF, 0, 0, 16 },
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Package(){0x0014FFFF, 1, 0, 17 },
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Package(){0x0014FFFF, 2, 0, 18 },
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Package(){0x0014FFFF, 3, 0, 19 },
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// D19: Integrated Sensor Hub
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Package(){0x0013FFFF, 0, 0, 20 },
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// D18: Thermal, UFS, SerialIo SPI 2
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Package(){0x0012FFFF, 0, 0, 16 },
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Package(){0x0012FFFF, 1, 0, 24 },
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Package(){0x0012FFFF, 2, 0, 18 },
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Package(){0x0012FFFF, 3, 0, 19 },
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// Host Bridge
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// P.E.G. Root Port D1F0
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Package(){0x0001FFFF, 0, 0, 16 },
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Package(){0x0001FFFF, 1, 0, 17 },
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Package(){0x0001FFFF, 2, 0, 18 },
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Package(){0x0001FFFF, 3, 0, 19 },
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// P.E.G. Root Port D1F1
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// P.E.G. Root Port D1F2
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// SA IGFX Device
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Package(){0x0002FFFF, 0, 0, 16 },
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// SA Thermal Device
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Package(){0x0004FFFF, 0, 0, 16 },
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// SA IPU Device
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Package(){0x0005FFFF, 0, 0, 16 },
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// SA GNA Device
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Package(){0x0008FFFF, 0, 0, 16 },
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})
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Name(PD04, Package(){
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 10 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR04, Package(){
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Package(){0x0000FFFF, 0, 0, 16 },
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Package(){0x0000FFFF, 1, 0, 17 },
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Package(){0x0000FFFF, 2, 0, 18 },
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Package(){0x0000FFFF, 3, 0, 19 },
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})
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Name(PD05, Package(){
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Package(){0x0000FFFF, 0, 0, 10 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR05, Package(){
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Package(){0x0000FFFF, 0, 0, 17 },
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Package(){0x0000FFFF, 1, 0, 18 },
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Package(){0x0000FFFF, 2, 0, 19 },
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Package(){0x0000FFFF, 3, 0, 16 },
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})
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Name(PD06, Package(){
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 10 },
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})
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Name(AR06, Package(){
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Package(){0x0000FFFF, 0, 0, 18 },
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Package(){0x0000FFFF, 1, 0, 19 },
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Package(){0x0000FFFF, 2, 0, 16 },
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Package(){0x0000FFFF, 3, 0, 17 },
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})
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Name(PD07, Package(){
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 10 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR07, Package(){
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Package(){0x0000FFFF, 0, 0, 19 },
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Package(){0x0000FFFF, 1, 0, 16 },
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Package(){0x0000FFFF, 2, 0, 17 },
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Package(){0x0000FFFF, 3, 0, 18 },
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})
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Name(PD08, Package(){
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 10 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR08, Package(){
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Package(){0x0000FFFF, 0, 0, 16 },
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Package(){0x0000FFFF, 1, 0, 17 },
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Package(){0x0000FFFF, 2, 0, 18 },
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Package(){0x0000FFFF, 3, 0, 19 },
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})
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Name(PD09, Package(){
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Package(){0x0000FFFF, 0, 0, 10 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR09, Package(){
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Package(){0x0000FFFF, 0, 0, 17 },
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Package(){0x0000FFFF, 1, 0, 18 },
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Package(){0x0000FFFF, 2, 0, 19 },
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Package(){0x0000FFFF, 3, 0, 16 },
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})
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Name(PD0E, Package(){
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 10 },
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})
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Name(AR0E, Package(){
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Package(){0x0000FFFF, 0, 0, 18 },
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Package(){0x0000FFFF, 1, 0, 19 },
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Package(){0x0000FFFF, 2, 0, 16 },
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Package(){0x0000FFFF, 3, 0, 17 },
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})
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Name(PD0F, Package(){
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 10 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR0F, Package(){
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Package(){0x0000FFFF, 0, 0, 19 },
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Package(){0x0000FFFF, 1, 0, 16 },
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Package(){0x0000FFFF, 2, 0, 17 },
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Package(){0x0000FFFF, 3, 0, 18 },
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})
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Name(PD02, Package(){
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 10 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR02, Package(){
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// P.E.G. Port Slot x16
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Package(){0x0000FFFF, 0, 0, 16 },
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Package(){0x0000FFFF, 1, 0, 17 },
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Package(){0x0000FFFF, 2, 0, 18 },
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Package(){0x0000FFFF, 3, 0, 19 },
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})
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Name(PD0A, Package(){
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// P.E.G. Port Slot x8
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Package(){0x0000FFFF, 0, 0, 10 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 11 },
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})
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Name(AR0A, Package(){
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// P.E.G. Port Slot x8
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Package(){0x0000FFFF, 0, 0, 17 },
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Package(){0x0000FFFF, 1, 0, 18 },
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Package(){0x0000FFFF, 2, 0, 19 },
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Package(){0x0000FFFF, 3, 0, 16 },
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})
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Name(PD0B, Package(){
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// P.E.G. Port Slot x4
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Package(){0x0000FFFF, 0, 0, 11 },
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Package(){0x0000FFFF, 1, 0, 11 },
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Package(){0x0000FFFF, 2, 0, 11 },
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Package(){0x0000FFFF, 3, 0, 10 },
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})
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Name(AR0B, Package(){
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// P.E.G. Port Slot x4
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Package(){0x0000FFFF, 0, 0, 18 },
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Package(){0x0000FFFF, 1, 0, 19 },
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Package(){0x0000FFFF, 2, 0, 16 },
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Package(){0x0000FFFF, 3, 0, 17 },
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})
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//---------------------------------------------------------------------------
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// Begin PCI tree object scope
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//---------------------------------------------------------------------------
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Device(PCI0) { // PCI Bridge "Host Bridge"
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Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
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Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
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Name(_SEG, 0)
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Name(_ADR, 0x00000000)
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Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
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Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
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Name(_UID, 0x0000) // Unique Bus ID, optional
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Method(_PRT,0) {
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If(PICM) {Return(AR00)} // APIC mode
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Return (PD00) // PIC Mode
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} // end _PRT
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Include("HostBus.asl")
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} // end PCI0 Bridge "Host Bridge"
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} // end _SB scope
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