373 lines
6.5 KiB
Plaintext
373 lines
6.5 KiB
Plaintext
/**@file
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Register/RegsUsb.h>
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External(\_SB.PCI0.XHC.PS0X, MethodObj)
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External(\_SB.PCI0.XHC.PS3X, MethodObj)
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External(\_SB.PCI0.XHC.RHUB.PS0X, MethodObj)
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External(\_SB.PCI0.XHC.RHUB.PS2X, MethodObj)
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External(\_SB.PCI0.XHC.RHUB.PS3X, MethodObj)
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External(\_SB.PCI0.XHC.RHUB.INIR, MethodObj)
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Scope(\_SB_.PCI0) {
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Device(XHC) {
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Name(_ADR, 0x00140000)
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OperationRegion(XPRT,PCI_Config,0x00,0x100)
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Field(XPRT,AnyAcc,NoLock,Preserve)
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{
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DVID, 16,
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Offset(0x10),
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XADL, 32,
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XADH, 32,
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Offset(R_XHCI_CFG_PCE), // 0xA2
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, 2,
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D3HE, 1, // D3_hot_en
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}
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//
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// XHCI controller _DSM method
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//
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Method(_DSM,4,serialized){
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ADBG("XHCI _DSM")
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If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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Return(Buffer() {0})
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}
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Method(_S3D, 0, NotSerialized)
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{
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Return(3)
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}
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Method(_S4D, 0, NotSerialized)
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{
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Return(3)
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}
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Method(_S3W, 0, NotSerialized)
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{
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Return(3)
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}
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Method(_S4W, 0, NotSerialized)
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{
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Return(3)
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}
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Method(_S0W, 0x0, NotSerialized)
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{
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Return(0x3)
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}
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Method(_PRW, 0) {
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Return(GPRW(0x6D, 4)) // can wakeup from S4 state
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}
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Method(_DSW, 3) {}
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Method(_INI) {
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If(CondRefOf(\_SB.PCI0.XHC.RHUB.INIR)) { // _INI for RTD3
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\_SB.PCI0.XHC.RHUB.INIR()
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}
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}
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//
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// USRA (USbR port Address), method for calculating address of first USBR port in XHCI controller
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//
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Method(USRA,0,Serialized) {
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If(LEqual(PCHS, PCHH)) { // PCH-H
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Return (15)
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} Else { // PCH-LP
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Return (11)
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}
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}
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//
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// SSPA (SuperSpeed Port Address), method for calculating address of first SS port in XHCI controller
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//
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Method(SSPA,0,Serialized) {
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If(LEqual(PCHS, PCHH)) { // PCH-H
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Return (17)
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} Else { // PCH-LP
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Return (13)
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}
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}
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Method(_PS0,0,Serialized)
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{
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If(LEqual(^DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC PS0 method if present
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//
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If(CondRefOf(\_SB.PCI0.XHC.PS0X))
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{
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\_SB.PCI0.XHC.PS0X()
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}
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}
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Method(_PS3,0,Serialized)
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{
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If(LEqual(^DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC PS3 method if present
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//
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If(CondRefOf(\_SB.PCI0.XHC.PS3X))
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{
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\_SB.PCI0.XHC.PS3X()
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}
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}
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//
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//
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// Check for XHCI switch UUID
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//
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// Arguments:
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// Arg0 (Buffer) : UUID
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//
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// Returns:
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// 1: It's valid UUID
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// 0: Invalid UUID
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//
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Method(CUID,1,Serialized) {
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If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) {
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Return(1)
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}
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Return(0)
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}
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Device(RHUB)
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{
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Name(_ADR, Zero)
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// PS0 Method for xHCI Root Hub
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Method(_PS0,0,Serialized)
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{
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If(LEqual(\_SB.PCI0.XHC.DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC.RHUB PS0 method if present.
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//
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If(CondRefOf(\_SB.PCI0.XHC.RHUB.PS0X))
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{
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//
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// Don't Set/Clear MODPHY if RTD3 is disable.
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//
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\_SB.CSD0(MODPHY_SPD_GATING_XHCI)
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\_SB.PCI0.XHC.RHUB.PS0X()
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}
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}
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// PS2 Method for xHCI Root Hub
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Method(_PS2,0,Serialized)
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{
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If(LEqual(\_SB.PCI0.XHC.DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC.RHUB PS2 method if present.
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//
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If(CondRefOf(\_SB.PCI0.XHC.RHUB.PS2X))
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{
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\_SB.PCI0.XHC.RHUB.PS2X()
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//
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// Don't Set/Clear MODPHY if RTD3 is disable.
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//
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\_SB.CSD3(MODPHY_SPD_GATING_XHCI)
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}
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}
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// PS3 Method for xHCI Root Hub
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Method(_PS3,0,Serialized)
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{
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If(LEqual(\_SB.PCI0.XHC.DVID,0xFFFF))
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{
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Return()
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}
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//
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// Call platform XHC.RHUB PS3 method if present.
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//
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If(CondRefOf(\_SB.PCI0.XHC.RHUB.PS3X))
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{
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\_SB.PCI0.XHC.RHUB.PS3X()
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//
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// Don't Set/Clear MODPHY if RTD3 is disable.
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//
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\_SB.CSD3(MODPHY_SPD_GATING_XHCI)
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}
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}
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//
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// High Speed Ports (without USBR)
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//
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Device(HS01)
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{
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Name(_ADR, 0x01)
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}
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Device(HS02)
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{
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Name(_ADR, 0x02)
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}
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Device(HS03)
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{
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Name(_ADR, 0x03)
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}
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Device(HS04)
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{
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Name(_ADR, 0x04)
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}
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Device(HS05)
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{
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Name(_ADR, 0x05)
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}
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Device(HS06)
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{
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Name(_ADR, 0x06)
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}
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Device(HS07)
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{
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Name(_ADR, 0x07)
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}
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Device(HS08)
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{
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Name(_ADR, 0x08)
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}
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Device(HS09)
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{
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Name(_ADR, 0x09)
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}
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Device(HS10)
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{
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Name(_ADR, 0x0A)
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}
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//
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// USBR port will be known as USBR instead of HS11 / HS15
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//
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Device(USR1)
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{
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Method(_ADR) { Return (Add(USRA(),0)) }
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}
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//
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// USBR port 2 will be known as USBR instead of HS12 / HS16
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//
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Device(USR2)
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{
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Method(_ADR) { Return (Add(USRA(),1)) }
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}
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//
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// Super Speed Ports
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//
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Device(SS01)
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{
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Method(_ADR) { Return (Add(SSPA(),0)) }
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}
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Device(SS02)
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{
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Method(_ADR) { Return (Add(SSPA(),1)) }
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}
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Device(SS03)
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{
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Method(_ADR) { Return (Add(SSPA(),2)) }
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}
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Device(SS04)
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{
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Method(_ADR) { Return (Add(SSPA(),3)) }
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}
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Device(SS05)
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{
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Method(_ADR) { Return (Add(SSPA(),4)) }
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}
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Device(SS06)
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{
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Method(_ADR) { Return (Add(SSPA(),5)) }
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}
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} // device rhub
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} // device xhc
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} //scope
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//
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// If PCH-H add additional ports
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//
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If(LEqual(PCHS,PCHH)) {
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Scope(\_SB_.PCI0.XHC.RHUB) {
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Device(HS11)
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{
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Name(_ADR, 0xB)
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}
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Device(HS12)
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{
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Name(_ADR, 0xC)
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}
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Device(HS13)
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{
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Name(_ADR, 0xD)
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}
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Device(HS14)
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{
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Name(_ADR, 0xE)
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}
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Device(SS07)
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{
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Method(_ADR) { Return (Add(SSPA(),6)) }
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}
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Device(SS08)
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{
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Method(_ADR) { Return (Add(SSPA(),7)) }
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}
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Device(SS09)
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{
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Method(_ADR) { Return (Add(SSPA(),8)) }
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}
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Device(SS10)
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{
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Method(_ADR) { Return (Add(SSPA(),9)) }
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}
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} //scope
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} // if
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