77 lines
1.5 KiB
Plaintext
77 lines
1.5 KiB
Plaintext
/**@file
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "Register/PchRegsClk.h"
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Scope(\_SB)
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{
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// IsCLK PCH register for clock settings
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OperationRegion (ICLK, SystemMemory, Add(SBRG, Add(ShiftLeft(PID_ICLK, 16), R_ICLK_PCR_CAMERA1)), 0x82)
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Field(ICLK,AnyAcc,Lock,Preserve)
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{
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CLK1, 8,
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Offset(0x80),
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CLK2, 8,
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}
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//
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// Number Of Clocks
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//
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Method(NCLK, 0x0, NotSerialized)
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{
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Return (2) // IMGCLKOUT_0, IMGCLKOUT_1
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}
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//
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// Clock Control
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//
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Method(CLKC, 0x2, NotSerialized)
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{
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//
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// Arg0 - Clock number (0:IMGCLKOUT_0, etc)
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// Arg1 - Desired state (0:Disable, 1:Enable)
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//
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Switch(Arg0)
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{
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Case (0)
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{
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Store(CLK1, Local0)
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Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK1)
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}
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Case (1)
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{
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Store(CLK2, Local0)
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Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK2)
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}
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}
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}
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//
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// Clock Frequency
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//
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Method(CLKF, 0x2, NotSerialized)
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{
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//
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// Arg0 - Clock number (0:IMGCLKOUT_0, etc)
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// Arg1 - Clock frequency (0:24MHz, 1:19.2MHz)
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//
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Switch(Arg0)
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{
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Case (0)
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{
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Store(CLK1, Local0)
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Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK1)
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}
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Case (1)
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{
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Store(CLK2, Local0)
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Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK2)
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}
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}
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}
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} // \_SB
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