808 lines
16 KiB
Plaintext
808 lines
16 KiB
Plaintext
/** @file
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This file contains the SystemAgent PCI Configuration space
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definition.
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It defines various System Agent PCI Configuration Space registers
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which will be used to dynamically produce all resources in the Host Bus.
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@note This ASL file needs to be included as part of platform ACPI DSDT table.
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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External(M64B)
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External(M64L)
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External(M32B)
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External(M32L)
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//
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// Define various System Agent (SA) PCI Configuration Space
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// registers which will be used to dynamically produce all
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// resources in the Host Bus _CRS.
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//
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OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
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Field (HBUS, DWordAcc, NoLock, Preserve)
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{
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Offset(0x40), // EPBAR (0:0:0:40)
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EPEN, 1, // Enable
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, 11,
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EPBR, 20, // EPBAR [31:12]
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Offset(0x48), // MCHBAR (0:0:0:48)
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MHEN, 1, // Enable
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, 14,
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MHBR, 17, // MCHBAR [31:15]
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Offset(0x50), // GGC (0:0:0:50)
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GCLK, 1, // GGCLCK
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Offset(0x54), // DEVEN (0:0:0:54)
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D0EN, 1, // DEV0 Enable
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D1F2, 1, // DEV1 FUN2 Enable
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D1F1, 1, // DEV1 FUN1 Enable
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D1F0, 1, // DEV1 FUN0 Enable
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#ifndef CPU_CFL
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, 9,
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D6F0, 1, // DEV6 FUN0 Enable
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#endif
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Offset(0x60), // PCIEXBAR (0:0:0:60)
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PXEN, 1, // Enable
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PXSZ, 2, // PCI Express Size
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, 23,
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PXBR, 6, // PCI Express BAR [31:26]
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Offset(0x68), // DMIBAR (0:0:0:68)
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DIEN, 1, // Enable
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, 11,
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DIBR, 20, // DMIBAR [31:12]
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Offset(0x70), // MESEG_BASE (0:0:0:70)
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, 20,
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MEBR, 12, // MESEG_BASE [31:20]
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Offset(0x80), // PAM0 Register (0:0:0:80)
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PMLK, 1, // PAM Lock bit.
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, 3,
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PM0H, 2, // PAM 0, High Nibble
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, 2,
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Offset(0x81), // PAM1 Register (0:0:0:81)
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PM1L, 2, // PAM1, Low Nibble
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, 2,
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PM1H, 2, // PAM1, High Nibble
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, 2,
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Offset(0x82), // PAM2 Register (0:0:0:82)
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PM2L, 2, // PAM2, Low Nibble
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, 2,
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PM2H, 2, // PAM2, High Nibble
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, 2,
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Offset(0x83), // PAM3 Register (0:0:0:83)
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PM3L, 2, // PAM3, Low Nibble
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, 2,
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PM3H, 2, // PAM3, High Nibble
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, 2,
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Offset(0x84), // PAM4 Register (0:0:0:84)
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PM4L, 2, // PAM4, Low Nibble
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, 2,
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PM4H, 2, // PAM4, High Nibble
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, 2,
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Offset(0x85), // PAM5 Register (0:0:0:85)
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PM5L, 2, // PAM5, Low Nibble
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, 2,
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PM5H, 2, // PAM5, High Nibble
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, 2,
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Offset(0x86), // PAM6 Register (0:0:0:86)
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PM6L, 2, // PAM6, Low Nibble
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, 2,
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PM6H, 2, // PAM6, High Nibble
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, 2,
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Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
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, 20,
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TUUD, 19, // TOUUD [38:20]
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Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
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, 20,
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TLUD, 12, // TOLUD [31:20]
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Offset(0xC8), // ERRSTS register (0:0:0:C8)
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, 7,
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HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR
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}
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//
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// Define a buffer that will store all the bus, memory, and IO information
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// relating to the Host Bus. This buffer will be dynamically altered in
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// the _CRS and passed back to the OS.
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//
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Name(BUF0,ResourceTemplate()
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{
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//
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// Bus Number Allocation: Bus 0 to 0xFF
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//
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WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
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0x0000,0x00FF,0x00,0x0100,,,PB00)
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//
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// I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
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//
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DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
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0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
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//
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// PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
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//
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Io(Decode16,0x0CF8,0x0CF8,1,0x08)
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//
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// I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
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//
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DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
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0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
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//
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// Video Buffer Area ( 0xA0000 - 0xBFFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
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//
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// ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
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//
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// ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
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//
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// ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
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//
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// ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
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//
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// ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
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//
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// ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
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//
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// ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
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//
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// ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
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//
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// BIOS Extension Area ( 0xE0000 - 0xE3FFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
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//
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// BIOS Extension Area ( 0xE4000 - 0xE7FFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
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//
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// BIOS Extension Area ( 0xE8000 - 0xEBFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
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//
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// BIOS Extension Area ( 0xEC000 - 0xEFFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
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//
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// BIOS Area ( 0xF0000 - 0xFFFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
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// //
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// // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
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// //
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// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
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// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
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//
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// PCI Memory Region ( TOLUD - 0xDFFFFFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
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ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01)
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//
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// PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
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// (This is dummy range for OS compatibility, will patch it in _CRS)
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//
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QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
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ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
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//
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// PCH reserved resources ( 0xFC800000 - 0xFE7FFFFF )
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//
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DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
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ReadWrite,0x00,0xFC800000,0xFE7FFFFF,0x00,0x2000000,,,PM03)
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})
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#ifdef CPU_CFL
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//
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// SA reserved resources
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//
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Device(SRRE) {
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Name(_HID,EISAID("PNP0C02")) // motherboard resource
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Name(_UID,"SARESV")
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Method(_STA,0,Serialized) // device present and decodes its resources, but not to be displayed in OSPM
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{
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If(LGreaterEqual(TLUD, 0x404)) {
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Return (3)
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} Else {
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Return (0)
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}
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}
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Method(_CRS,0,Serialized)
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{
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Name(BUF0,ResourceTemplate(){
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//
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// Reserve the 0x40000000 ~ 0x403FFFFF to prevent other driver use this memory range
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//
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Memory32Fixed(ReadOnly,0x40000000,0x400000)
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})
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If(LGreaterEqual(TLUD, 0x404)) {
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Return (BUF0)
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} Else {
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Return (Buffer(){})
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}
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}
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}
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#endif
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Name(EP_B, 0) // to store EP BAR
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Name(MH_B, 0) // to store MCH BAR
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Name(PC_B, 0) // to store PCIe BAR
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Name(PC_L, 0) // to store PCIe BAR Length
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Name(DM_B, 0) // to store DMI BAR
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//
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// Get EP BAR
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//
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Method(GEPB,0,Serialized)
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{
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if(LEqual(EP_B,0))
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{
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ShiftLeft(\_SB.PCI0.EPBR,12,EP_B)
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}
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Return(EP_B)
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}
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//
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// Get MCH BAR
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//
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Method(GMHB,0,Serialized)
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{
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if(LEqual(MH_B,0))
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{
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ShiftLeft(\_SB.PCI0.MHBR,15,MH_B)
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}
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Return(MH_B)
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}
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//
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// Get PCIe BAR
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//
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Method(GPCB,0,Serialized)
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{
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if(LEqual(PC_B,0))
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{
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ShiftLeft(\_SB.PCI0.PXBR,26,PC_B)
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}
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Return(PC_B)
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}
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//
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// Get PCIe Length
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//
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Method(GPCL,0,Serialized)
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{
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if(LEqual(PC_L,0)) {
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ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L)
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}
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Return(PC_L)
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}
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//
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// Get DMI BAR
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//
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Method(GDMB,0,Serialized)
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{
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if(LEqual(DM_B,0))
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{
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ShiftLeft(\_SB.PCI0.DIBR,12,DM_B)
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}
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Return(DM_B)
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}
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Method(_CRS,0,Serialized)
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{
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//
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// Fix up Max Bus Number and Length
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//
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Store(\_SB.PCI0.GPCL(),Local0)
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CreateWordField(BUF0, ^PB00._MAX, PBMX)
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Store(Subtract(ShiftRight(Local0,20),2), PBMX)
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CreateWordField(BUF0, ^PB00._LEN, PBLN)
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Store(Subtract(ShiftRight(Local0,20),1), PBLN)
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//
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// Fix up all of the Option ROM areas from 0xC0000-0xFFFFF.
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//
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If(PM1L) // \_SB.PCI0
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{
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// PAMx != 0. Set length = 0.
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CreateDwordField(BUF0, ^C000._LEN,C0LN)
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Store(Zero,C0LN)
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}
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If(LEqual(PM1L,1))
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{
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CreateBitField(BUF0, ^C000._RW,C0RW)
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Store(Zero,C0RW)
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}
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If(PM1H)
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{
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CreateDwordField(BUF0, ^C400._LEN,C4LN)
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Store(Zero,C4LN)
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}
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If(LEqual(PM1H,1))
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{
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CreateBitField(BUF0, ^C400._RW,C4RW)
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Store(Zero,C4RW)
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}
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If(PM2L)
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{
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CreateDwordField(BUF0, ^C800._LEN,C8LN)
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Store(Zero,C8LN)
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}
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If(LEqual(PM2L,1))
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{
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CreateBitField(BUF0, ^C800._RW,C8RW)
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Store(Zero,C8RW)
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}
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If(PM2H)
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{
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CreateDwordField(BUF0, ^CC00._LEN,CCLN)
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Store(Zero,CCLN)
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}
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If(LEqual(PM2H,1))
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{
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CreateBitField(BUF0, ^CC00._RW,CCRW)
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Store(Zero,CCRW)
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}
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If(PM3L)
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{
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CreateDwordField(BUF0, ^D000._LEN,D0LN)
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Store(Zero,D0LN)
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}
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If(LEqual(PM3L,1))
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{
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CreateBitField(BUF0, ^D000._RW,D0RW)
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Store(Zero,D0RW)
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}
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If(PM3H)
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{
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CreateDwordField(BUF0, ^D400._LEN,D4LN)
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Store(Zero,D4LN)
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}
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If(LEqual(PM3H,1))
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{
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CreateBitField(BUF0, ^D400._RW,D4RW)
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Store(Zero,D4RW)
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}
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If(PM4L)
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{
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CreateDwordField(BUF0, ^D800._LEN,D8LN)
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Store(Zero,D8LN)
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}
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If(LEqual(PM4L,1))
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{
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CreateBitField(BUF0, ^D800._RW,D8RW)
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Store(Zero,D8RW)
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}
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If(PM4H)
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{
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CreateDwordField(BUF0, ^DC00._LEN,DCLN)
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Store(Zero,DCLN)
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}
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If(LEqual(PM4H,1))
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{
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CreateBitField(BUF0, ^DC00._RW,DCRW)
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Store(Zero,DCRW)
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}
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If(PM5L)
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{
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CreateDwordField(BUF0, ^E000._LEN,E0LN)
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Store(Zero,E0LN)
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}
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If(LEqual(PM5L,1))
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{
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CreateBitField(BUF0, ^E000._RW,E0RW)
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Store(Zero,E0RW)
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}
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If(PM5H)
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{
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CreateDwordField(BUF0, ^E400._LEN,E4LN)
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Store(Zero,E4LN)
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}
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If(LEqual(PM5H,1))
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{
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CreateBitField(BUF0, ^E400._RW,E4RW)
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Store(Zero,E4RW)
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}
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If(PM6L)
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{
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CreateDwordField(BUF0, ^E800._LEN,E8LN)
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Store(Zero,E8LN)
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}
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If(LEqual(PM6L,1))
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{
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CreateBitField(BUF0, ^E800._RW,E8RW)
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Store(Zero,E8RW)
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}
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If(PM6H)
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{
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CreateDwordField(BUF0, ^EC00._LEN,ECLN)
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Store(Zero,ECLN)
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}
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If(LEqual(PM6H,1))
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{
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CreateBitField(BUF0, ^EC00._RW,ECRW)
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Store(Zero,ECRW)
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}
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If(PM0H)
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{
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CreateDwordField(BUF0, ^F000._LEN,F0LN)
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Store(Zero,F0LN)
|
|
}
|
|
|
|
If(LEqual(PM0H,1))
|
|
{
|
|
CreateBitField(BUF0, ^F000._RW,F0RW)
|
|
Store(Zero,F0RW)
|
|
}
|
|
|
|
// Enable the 1MB region between 15-16MB if HENA = 1.
|
|
//
|
|
// If( MCHC.HENA)
|
|
// {
|
|
// CreateDwordField(BUF0, HOLE._LEN,H0LN)
|
|
// Store(0x100000,H0LN)
|
|
// }
|
|
|
|
//
|
|
// Create pointers to Memory Sizing values.
|
|
//
|
|
CreateDwordField(BUF0, ^PM01._MIN,M1MN)
|
|
CreateDwordField(BUF0, ^PM01._MAX,M1MX)
|
|
CreateDwordField(BUF0, ^PM01._LEN,M1LN)
|
|
|
|
//
|
|
// Set Memory Size Values. TLUD represents bits 31:20 of phyical
|
|
// TOM, so shift these bits into the correct position and fix up
|
|
// the Memory Region available to PCI.
|
|
//
|
|
Store (M32L, M1LN)
|
|
Store (M32B, M1MN)
|
|
Subtract (Add (M1MN, M1LN), 1, M1MX)
|
|
|
|
//
|
|
// Create pointers to Memory Sizing values.
|
|
// Patch PM02 range basing on memory size and OS type
|
|
//
|
|
If (LEqual(M64L, 0)) {
|
|
CreateQwordField(BUF0, ^PM02._LEN,MSLN)
|
|
//
|
|
// Set resource length to 0
|
|
//
|
|
Store (0, MSLN)
|
|
}
|
|
Else {
|
|
CreateQwordField(BUF0, ^PM02._LEN,M2LN)
|
|
CreateQwordField(BUF0, ^PM02._MIN,M2MN)
|
|
CreateQwordField(BUF0, ^PM02._MAX,M2MX)
|
|
//
|
|
// Set 64bit MMIO resource Base and Length
|
|
//
|
|
Store (M64L, M2LN)
|
|
Store (M64B, M2MN)
|
|
Subtract (Add (M2MN, M2LN), 1, M2MX)
|
|
}
|
|
Return(BUF0)
|
|
}
|
|
|
|
//
|
|
//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
|
|
//
|
|
Name(GUID,Buffer(){0x5b, 0x4d, 0xdb, 0x33,
|
|
0xf7, 0x1f,
|
|
0x1c, 0x40,
|
|
0x96, 0x57,
|
|
0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66})
|
|
|
|
|
|
Name(SUPP,0) // PCI _OSC Support Field value
|
|
Name(CTRL,0) // PCI _OSC Control Field value
|
|
Name(XCNT, 0) // Variable used in _OSC for counting
|
|
|
|
Method(_OSC,4,Serialized)
|
|
{
|
|
//
|
|
// Check for proper UUID
|
|
// Save the capabilities buffer
|
|
//
|
|
Store(Arg3,Local0)
|
|
|
|
//
|
|
// Create DWord-adressable fields from the Capabilties Buffer
|
|
//
|
|
CreateDWordField(Local0,0,CDW1)
|
|
CreateDWordField(Local0,4,CDW2)
|
|
CreateDWordField(Local0,8,CDW3)
|
|
|
|
//
|
|
// Check for proper UUID
|
|
//
|
|
If(LEqual(Arg0,GUID))
|
|
{
|
|
// Save Capabilities DWord2 & 3
|
|
Store(CDW2,SUPP)
|
|
Store(CDW3,CTRL)
|
|
|
|
//
|
|
// You can clear bits in CTRL here if you don't want OS to take
|
|
// control
|
|
//
|
|
If(LNot(NEXP))
|
|
{
|
|
And(CTRL, 0xFFFFFFF8, CTRL) // disable Native hot plug, PME
|
|
}
|
|
|
|
If(Not(And(CDW1,1))) // Query flag clear?
|
|
{ // Disable GPEs for features granted native control.
|
|
If(And(CTRL,0x01))
|
|
{
|
|
NHPG()
|
|
}
|
|
If(And(CTRL,0x04)) // PME control granted?
|
|
{
|
|
NPME()
|
|
}
|
|
}
|
|
|
|
If(LNotEqual(Arg1,One))
|
|
{
|
|
//
|
|
// Unknown revision
|
|
//
|
|
Or(CDW1,0x08,CDW1)
|
|
}
|
|
|
|
If(LNotEqual(CDW3,CTRL))
|
|
{
|
|
//
|
|
// Capabilities bits were masked
|
|
//
|
|
Or(CDW1,0x10,CDW1)
|
|
}
|
|
//
|
|
// Update DWORD3 in the buffer
|
|
//
|
|
Store(CTRL,CDW3)
|
|
Store(CTRL,OSCC)
|
|
Return(Local0)
|
|
} Else {
|
|
Or(CDW1,4,CDW1) // Unrecognized UUID
|
|
Return(Local0)
|
|
}
|
|
} // End _OSC
|
|
|
|
//
|
|
// Added code for Dual IRQ support. Two set of ACPI IRQ tables were generated.
|
|
// Code has been added to select the appropriate IRQ table by checking the CPUID.
|
|
//
|
|
Scope(\_SB.PCI0)
|
|
{
|
|
Method(AR00) {
|
|
Return(\_SB.AR00)
|
|
}
|
|
|
|
Method(PD00) {
|
|
Return(\_SB.PD00)
|
|
}
|
|
|
|
Method(AR02) {
|
|
Return(\_SB.AR02)
|
|
}
|
|
|
|
Method(PD02) {
|
|
Return(\_SB.PD02)
|
|
}
|
|
|
|
Method(AR04) {
|
|
Return(\_SB.AR04)
|
|
}
|
|
|
|
Method(PD04) {
|
|
Return(\_SB.PD04)
|
|
}
|
|
|
|
Method(AR05) {
|
|
Return(\_SB.AR05)
|
|
}
|
|
|
|
Method(PD05) {
|
|
Return(\_SB.PD05)
|
|
}
|
|
|
|
Method(AR06) {
|
|
Return(\_SB.AR06)
|
|
}
|
|
|
|
Method(PD06) {
|
|
Return(\_SB.PD06)
|
|
}
|
|
|
|
Method(AR07) {
|
|
Return(\_SB.AR07)
|
|
}
|
|
|
|
Method(PD07) {
|
|
Return(\_SB.PD07)
|
|
}
|
|
|
|
Method(AR08) {
|
|
Return(\_SB.AR08)
|
|
}
|
|
|
|
Method(PD08) {
|
|
Return(\_SB.PD08)
|
|
}
|
|
|
|
Method(AR09) {
|
|
Return(\_SB.AR09)
|
|
}
|
|
|
|
Method(PD09) {
|
|
Return(\_SB.PD09)
|
|
}
|
|
|
|
Method(AR0A) {
|
|
Return(\_SB.AR0A)
|
|
}
|
|
|
|
Method(PD0A) {
|
|
Return(\_SB.PD0A)
|
|
}
|
|
|
|
Method(AR0B) {
|
|
Return(\_SB.AR0B)
|
|
}
|
|
|
|
Method(PD0B) {
|
|
Return(\_SB.PD0B)
|
|
}
|
|
|
|
//
|
|
// Add device scope definition for System Agent
|
|
// P.E.G. Root Port D1F0
|
|
//
|
|
Device(PEG0) {
|
|
Name(_ADR, 0x00010000)
|
|
Device(PEGP) { // P.E.G. Port Slot x16
|
|
Name(_ADR, 0x00000000)
|
|
}
|
|
}
|
|
//
|
|
// P.E.G. Root Port D1F1
|
|
//
|
|
Device(PEG1) {
|
|
Name(_ADR, 0x00010001)
|
|
Device(PEGP) { // P.E.G. Port Slot x8
|
|
Name(_ADR, 0x00000000)
|
|
}
|
|
}
|
|
//
|
|
// P.E.G. Root Port D1F2
|
|
//
|
|
Device(PEG2) {
|
|
Name(_ADR, 0x00010002)
|
|
Device(PEGP) { // P.E.G. Port Slot x4
|
|
Name(_ADR, 0x00000000)
|
|
}
|
|
}
|
|
#ifndef CPU_CFL
|
|
//
|
|
// P.E.G. Root Port D6F0
|
|
//
|
|
Device(PEG3) {
|
|
Name(_ADR, 0x00060000)
|
|
Device(PEGP) { // P.E.G. Port Slot x4
|
|
Name(_ADR, 0x00000000)
|
|
}
|
|
}
|
|
#endif
|
|
//
|
|
// I.G.D
|
|
//
|
|
Device(GFX0) {
|
|
Name(_ADR, 0x00020000)
|
|
}
|
|
//
|
|
// SA Thermal Device
|
|
//
|
|
Device(B0D4) {
|
|
Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; Return(Buffer() {0})}
|
|
Name(_ADR, 0x00040000)
|
|
}
|
|
//
|
|
// Device IPU0 is the IPU PCI device
|
|
//
|
|
Device(IPU0) {
|
|
Name(_ADR, 0x00050000)
|
|
}
|
|
}
|