88 lines
5.3 KiB
Plaintext
88 lines
5.3 KiB
Plaintext
/**@file
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Define CPU NVS Area operation region.
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//
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OperationRegion(PNVS,SystemMemory,0xFFFF0000,0xAA55)
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Field(PNVS,AnyAcc,Lock,Preserve)
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{ Offset(0), PGRV, 8, // Offset(0), CPU GlobalNvs Revision
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Offset(1), CFGD, 32, // Offset(1), PPM Flags Values
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Offset(6), // Offset(5) : Offset(5), Reserved bytes
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Offset(6), ACRT, 8, // Offset(6), Auto Critical Trip Point
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Offset(7), APSV, 8, // Offset(7), Auto Passive Trip Point
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Offset(8), AAC0, 8, // Offset(8), Auto Active Trip Point
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Offset(9), CPID, 32, // Offset(9), CPUID
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Offset(13), CPPC, 8, // Offset(13), Boot Mode vlues for _PPC
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Offset(14), CLVL, 8, // Offset(14), ConfigTdp Number Of Levels
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Offset(15), CBMI, 8, // Offset(15), CTDP Boot Mode Index
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Offset(16), PL10, 16, // Offset(16), CTDP Level 0 Power Limit1
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Offset(18), PL11, 16, // Offset(18), CTDP Level 1 Power Limit1
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Offset(20), PL12, 16, // Offset(20), CTDP Level 2 Power Limit1
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Offset(22), PL20, 16, // Offset(22), CTDP Level 0 Power Limit2
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Offset(24), PL21, 16, // Offset(24), CTDP Level 1 Power Limit2
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Offset(26), PL22, 16, // Offset(26), CTDP Level 2 Power Limit2
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Offset(28), PLW0, 8, // Offset(28), CTDP Level 0 Power Limit1 Time Window
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Offset(29), PLW1, 8, // Offset(29), CTDP Level 1 Power Limit1 Time Window
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Offset(30), PLW2, 8, // Offset(30), CTDP Level 2 Power Limit1 Time Window
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Offset(31), CTC0, 8, // Offset(31), CTDP Level 0 CTC
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Offset(32), CTC1, 8, // Offset(32), CTDP Level 1 CTC
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Offset(33), CTC2, 8, // Offset(33), CTDP Level 2 CTC
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Offset(34), TAR0, 8, // Offset(34), CTDP Level 0 TAR
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Offset(35), TAR1, 8, // Offset(35), CTDP Level 1 TAR
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Offset(36), TAR2, 8, // Offset(36), CTDP Level 2 TAR
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Offset(37), PPC0, 8, // Offset(37), CTDP Level 0 PPC
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Offset(38), PPC1, 8, // Offset(38), CTDP Level 1 PPC
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Offset(39), PPC2, 8, // Offset(39), CTDP Level 2 PPC
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Offset(41), // Offset(40) : Offset(40), Reserved bytes
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Offset(41), C6MW, 8, // Offset(41), Mwait Hint value for C6
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Offset(42), C7MW, 8, // Offset(42), Mwait Hint value for C7/C7s
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Offset(43), CDMW, 8, // Offset(43), Mwait Hint value for C7/C8/C9/C10
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Offset(46), // Offset(44) : Offset(45), Reserved bytes
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Offset(46), C6LT, 16, // Offset(46), Latency Value for C6
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Offset(48), C7LT, 16, // Offset(48), Latency Value for C7/C7S
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Offset(50), CDLT, 16, // Offset(50), Latency Value for C8/C9/C10
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Offset(52), CDLV, 16, // Offset(52), IO LVL value for C8/C9/C10
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Offset(54), CDPW, 16, // Offset(54), Power value for C8/C9/C10
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Offset(56), MPMF, 8, // Offset(56), MiscPowerManagementFlags
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Offset(57), DTSE, 8, // Offset(57), Digital Thermal Sensor Enable
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Offset(58), DTS1, 8, // Offset(58), Digital Thermal Sensor 1 Readingn for BSP
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Offset(59), DTS2, 8, // Offset(59), Digital Thermal Sensor 2 Reading for AP1
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Offset(60), DTSF, 8, // Offset(60), DTS SMI Function Call via DTS IO Trap
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Offset(61), PDTS, 8, // Offset(61), Package Temperature
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Offset(62), PKGA, 8, // Offset(62), Package Temperature MSR available
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Offset(63), DTS3, 8, // Offset(63), Digital Thermal Sensor 3 Reading for AP2
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Offset(64), DTS4, 8, // Offset(64), Digital Thermal Sensor 4 Reading for AP3
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Offset(65), BGMA, 64, // Offset(65), BIOS Guard Memory Address for Tool Interface
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Offset(73), BGMS, 8, // Offset(73), BIOS Guard Memory Size for Tool Interface
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Offset(74), BGIA, 16, // Offset(74), BIOS Guard IoTrap Address for Tool Interface
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Offset(76), BGIL, 16, // Offset(76), BIOS Guard IoTrap Length for Tool Interface
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Offset(78), DSIA, 16, // Offset(78), DTS IO trap Address
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Offset(80), DSIL, 8, // Offset(80), DTS IO trap Length
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Offset(81), DSAE, 8, // Offset(81), DTS is in ACPI Mode Enabled
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Offset(82), EPCS, 8, // Offset(82), SGX Status
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Offset(83), EMNA, 64, // Offset(83), EPC Base Address
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Offset(91), ELNG, 64, // Offset(91), EPC Length
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Offset(99), HWPV, 8, // Offset(99), HWP Version
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Offset(100), HWPI, 8, // Offset(100), HWP Interrupt Status
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Offset(101), DTSI, 8, // Offset(101), DTS Interrupt Status
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Offset(102), HWPS, 8, // Offset(102), SMI to setup HWP LVT tables
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Offset(103), LMPS, 8, // Offset(103), Max ratio of the slowest core.
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Offset(104), ITBM, 8, // Offset(104), Enable/Disable Intel Turbo Boost Max Technology 3.0.
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Offset(105), ITBD, 8, // Offset(105), Enable/Disable Intel Turbo Boost Max Technology 3.0 Driver.
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Offset(106), ITBI, 8, // Offset(106), Intel Turbo Boost Max Technology 3.0 interrupt status.
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Offset(107), ITBS, 8, // Offset(107), SMI to resume periodic SMM for Intel Turbo Boost Max Technology 3.0.
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Offset(108), OBIN, 8, // Offset(108), Indicates bins of Oc support. MSR 194h FLEX_RATIO Bits (19:17)
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#ifdef CPU_CFL
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Offset(109), C3MW, 8, // Offset(109), Mwait Hint value for C3 (CFL only)
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Offset(110), C3LT, 16, // Offset(110), Latency Value for C3 (CFL only)
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#endif
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}
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