224 lines
9.1 KiB
Plaintext
224 lines
9.1 KiB
Plaintext
/** @file
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ACPI DSDT table
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Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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Scope(\_SB)
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{
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Processor(PR00, // Unique name for Processor 0.
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1, // Unique ID for Processor 0.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR01, // Unique name for Processor 1.
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2, // Unique ID for Processor 1.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR02, // Unique name for Processor 2.
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3, // Unique ID for Processor 2.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR03, // Unique name for Processor 3.
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4, // Unique ID for Processor 3.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR04, // Unique name for Processor 4.
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5, // Unique ID for Processor 4.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR05, // Unique name for Processor 5.
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6, // Unique ID for Processor 5.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR06, // Unique name for Processor 6.
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7, // Unique ID for Processor 6.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR07, // Unique name for Processor 7.
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8, // Unique ID for Processor 7.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR08, // Unique name for Processor 8.
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9, // Unique ID for Processor 8.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR09, // Unique name for Processor 9.
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10, // Unique ID for Processor 9.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR10, // Unique name for Processor 10.
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11, // Unique ID for Processor 10.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR11, // Unique name for Processor 11.
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12, // Unique ID for Processor 11.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR12, // Unique name for Processor 12.
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13, // Unique ID for Processor 12.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR13, // Unique name for Processor 13.
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14, // Unique ID for Processor 13.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR14, // Unique name for Processor 14.
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15, // Unique ID for Processor 14.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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Processor(PR15, // Unique name for Processor 15.
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16, // Unique ID for Processor 15.
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0x1810, // P_BLK address = ACPIBASE + 10h.
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6) // P_BLK length = 6 bytes.
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{}
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} // End Scope(\_SB)
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Scope(\_SB.PR00)
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{
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Name(CPC2, Package()
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{
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21, // Number of entries
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02, // Revision
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//
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// Describe processor capabilities
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//
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ResourceTemplate() {Register(FFixedHW, 8, 0, 0x771, 4)}, // HighestPerformance
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ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
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ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
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ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
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ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
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ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
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ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
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ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
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ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
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ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
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ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
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ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
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ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
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ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
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ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
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1, // Autonomous selection enable register (Exclusively autonomous)
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ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
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ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
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0 // Reference performance (not supported)
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})
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Name(CPOC, Package()
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{
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21, // Number of entries
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02, // Revision
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//
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// Describe processor capabilities
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//
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255, // HighestPerformance
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ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Performance - Maximum Non Turbo Ratio
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ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonlinear Performance
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ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPerformance
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ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guaranteed Performance
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ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired PerformanceRegister
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ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum PerformanceRegister
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ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum PerformanceRegister
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ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performance ReductionToleranceRegister (Null)
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ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time window register(Null)
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ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wrap around time(Null)
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ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference counter register (PPERF)
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ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered counter register (APERF)
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ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performance limited register
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ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable register
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1, // Autonomous selection enable register (Exclusively autonomous)
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ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomous activity window register
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ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomous energy performance preference register
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0 // Reference performance (not supported)
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})
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}// end Scope(\_SB.PR00)
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#ifndef SPS_SUPPORT // SPS is using Processor Aggregator Device different way
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Scope(\_SB)
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{
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// The Processor Aggregator Device provides a control point that enables the platform to perform
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// specific processor configuration and control that applies to all processors in the platform.
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Device (PAGD)
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{
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Name (_HID, "ACPI000C") // Processor Aggregator Device
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// _STA (Status)
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//
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// This object returns the current status of a device.
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//
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// Arguments: (0)
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// None
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// Return Value:
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// An Integer containing a device status bitmap:
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// Bit 0 - Set if the device is present.
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// Bit 1 - Set if the device is enabled and decoding its resources.
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// Bit 2 - Set if the device should be shown in the UI.
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// Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics).
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// Bit 4 - Set if the battery is present.
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// Bits 5-31 - Reserved (must be cleared).
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//
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Method(_STA)
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{
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If(\_OSI("Processor Aggregator Device")){
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Return (0x0F) // Processor Aggregator Device is supported by this OS.
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} Else {
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Return (0) // No support in this OS.
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}
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}
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// _PUR (Processor Utilization Request)
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//
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// The _PUR object is an optional object that may be declared under the Processor Aggregator Device
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// and provides a means for the platform to indicate to OSPM the number of logical processors
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// to be idled. OSPM evaluates the _PUR object as a result of the processing of a Notify event
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// on the Processor Aggregator device object of type 0x80.
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//
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// Arguments: (0)
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// None
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// Return Value:
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// Package
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//
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Name (_PUR, Package() // Requests a number of logical processors to be placed in an idle state.
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{
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1, // RevisionID, Integer: Current value is 1
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0 // NumProcessors, Integer
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})
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} // end Device(PAGD)
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}// end Scope(\_SB)
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#endif // ndef SPS_SUPPORT
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