240 lines
8.9 KiB
YAML
240 lines
8.9 KiB
YAML
## @file
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#
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# Slim Bootloader CFGDATA Option File.
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#
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# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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- $ACTION :
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page : SIL
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- SILICON_CFG_DATA :
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- !expand { CFGHDR_TMPL : [ SILICON_CFG_DATA, 0x500, 0, 0 ] }
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- !expand { SIL_TMPL : [ SATA CFG 0] }
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- SataConfig0 :
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- $STRUCT :
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name : Sata Configuration 0
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help : >
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Configure SATA Configuration Features
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struct : SATA_FEATURE_CFG_0
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length : 0x04
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- EnableSATA0 :
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name : SATA Controller 0
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type : Combo
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option : $EN_DIS
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help : >
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Enable/disable SATA Controller 0.
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length : 1b
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value : 1
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- EnableSATA1 :
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name : SATA Controller 1
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type : Combo
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option : $EN_DIS
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help : >
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Enable/disable SATA Controller 1.
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length : 1b
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value : 1
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- EnableSATA2 :
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name : SATA Controller 2
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type : Combo
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option : $EN_DIS
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help : >
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Enable/disable SATA Controller 2.
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length : 1b
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value : 1
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- SATA0Mode :
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name : SATA Controller 0 Mode
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type : Combo
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option : 0:AHCI, 1:RAID
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help : >
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Mode of SATA Controller 0.
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length : 1b
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- SATA1Mode :
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name : SATA Controller 1 Mode
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type : Combo
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option : 0:AHCI, 1:RAID
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help : >
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Mode of SATA Controller 1.
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length : 1b
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- SATA2Mode :
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name : SATA Controller 2 Mode
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type : Combo
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option : 0:AHCI, 1:RAID
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help : >
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Mode of SATA Controller 2.
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length : 1b
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- SATA0IntMode :
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name : SATA Controller 0 Interrupt Mode
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type : Combo
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option : 0:Msix, 1:Msi, 2:Legacy
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help : >
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Interrupt Mode for SATA Controller 0.
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length : 2b
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- SATA1IntMode :
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name : SATA Controller 1 Interrupt Mode
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type : Combo
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option : 0:Msix, 1:Msi, 2:Legacy
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help : >
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Interrupt Mode for SATA Controller 1.
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length : 2b
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- SATA2IntMode :
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name : SATA Controller 2 Interrupt Mode
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type : Combo
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option : 0:Msix, 1:Msi, 2:Legacy
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help : >
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Interrupt Mode for SATA Controller 2.
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length : 2b
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- SATA0PortEnable :
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name : SATA Controller 0 Port Enable
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type : EditNum, Hex, (0x00, 0xFF)
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help : >
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Each one of 8 ports is represented by a bit. 0 : Disbaled, 1: Enabled
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length : 8b
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value : 0xFF
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- SATA0PortHotplug :
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name : SATA Controller 0 Port Hotplug capability
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type : EditNum, Hex, (0x00, 0xFF)
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help : >
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Each one of 8 ports is represented by a bit. 0 : Disbaled, 1: Enabled
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length : 8b
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value : 0
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- Reserved0 :
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name : Reserved0
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type : Reserved
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help : >
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Reserved
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length : 4b
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value : 0
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- !expand { SIL_TMPL : [ SATA CFG 1] }
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- SataConfig1 :
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- $STRUCT :
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name : Sata Configuration 1
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help : >
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Configure SATA Configuration Features
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struct : SATA_FEATURE_CFG_1
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length : 0x04
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- SATA1PortEnable :
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name : SATA Controller 1 Port Enable
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type : EditNum, Hex, (0x00, 0xFF)
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help : >
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Each one of 8 ports is represented by a bit. 0 : Disbaled, 1: Enabled
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length : 8b
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value : 0xFF
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- SATA1PortHotplug :
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name : SATA Controller 1 Port Hotplug capability
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type : EditNum, Hex, (0x00, 0xFF)
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help : >
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Each one of 8 ports is represented by a bit. 0 : Disbaled, 1: Enabled
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length : 8b
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value : 0
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- SATA2PortEnable :
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name : SATA Controller 2 Port Enable
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type : EditNum, Hex, (0x00, 0xFF)
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help : >
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Each one of 8 ports is represented by a bit. 0 : Disbaled, 1: Enabled
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length : 8b
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value : 0xFF
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- SATA2PortHotplug :
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name : SATA Controller 2 Port Hotplug capability
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type : EditNum, Hex, (0x00, 0xFF)
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help : >
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Each one of 8 ports is represented by a bit. 0 : Disbaled, 1: Enabled
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length : 8b
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value : 0
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- !expand { SIL_TMPL : [ FPRR ] }
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- FprrConfig :
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- $STRUCT :
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name : FPRR Configuration
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help : >
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Configure Silicon Configuration Features
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struct : FPRR_CFG
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length : 0x20
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- WriteEnable :
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name : PCH Flash Protection Ranges Write Enable
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type : EditNum, HEX, (0x00,0xFFFFFFFFFFFF)
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help : >
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Each byte represents a WriteProtectionEnable for respective Range.
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length : 5
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value : { 0x1, 0x1, 0x1, 0x1, 0x1 }
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- ReadEnable :
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name : PCH Flash Protection Ranges Read Enable
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type : EditNum, HEX, (0x00,0xFFFFFFFFFFFF)
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help : >
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Each byte represents a ReadProtectionEnable for respective Range.
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length : 5
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value : { 0x0, 0x0, 0x0, 0x0, 0x0 }
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- FprrRsvd :
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name : Reserved0
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type : Reserved
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help : >
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Reserved for padding.
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length : 2
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value : { 0x0, 0x0 }
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- Range :
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name : Base and Limit for Range [0..4]
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type : EditNum, HEX, (0x00,0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
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help : >
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Lower WORD is Base, Upper WORD is Limit.
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Base and Limit are left shifted address by 12 bits with Flash address.
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ex) 64MB SPI : (0x0000000-0x3FFFFFF) => (0x0000-0x3FFF).
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12MB BIOS: (0x3400000-0x3FFFFFF) => (0x3400-0x3FFF).
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struct : UINT32
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length : 0x14
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value : {0:0D, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
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- !expand { SIL_TMPL : [ INT Config ] }
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- IntConfig :
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- $STRUCT :
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name : Misc Configuration
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help : >
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Configure Silicon Configuration Features
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struct : INT_CFG
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length : 0x10
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- DevIntCfgptr :
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name : Address of PCH_DEVICE_INTERRUPT_CONFIG table.
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type : EditNum, HEX, (0x00, 0xFFFFFFFF)
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help : >
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The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
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length : 32b
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value : 0
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- GpioIrqRoute :
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name : Interrupt config GpioIrqRoute.
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type : EditNum, HEX, (0,0xFF)
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help : >
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GpioIrqRoute can be confiured here. Valid value should be set.
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length : 8b
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value : 0x15
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- SciIrqSelect :
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name : Interrupt config SciIrqSelect.
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type : EditNum, HEX, (0,0xFF)
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help : >
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SciIrqSelect can be confiured here. Valid value should be set.
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length : 8b
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value : 0x9
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- Reserved0 :
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name : Reserved0
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type : Reserved
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help : >
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Reserved
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length : 16b
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value : 0
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- PxRcConfig0 :
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name : Interrupt config PxRcConfig.
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type : EditNum, HEX, (0,0xFFFFFFFF)
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help : >
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PxRcConfig can be confiured here for PIRQA, PIRQB, PIRQC, PIRQD. First byte is for PIRQA, second byte is for PIRQB, and so on.
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length : 32b
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value : 0x0B0B0A0B
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- PxRcConfig1 :
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name : Interrupt config PxRcConfig.
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type : EditNum, HEX, (0,0xFFFFFFFF)
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help : >
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PxRcConfig can be confiured here for PIRQE, PIRQF, PIRQG, PIRQH. First byte is for PIRQE, second byte is for PIRQF, and so on.
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length : 32b
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value : 0x0B0B0B0B
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- Dummy :
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length : 0x0
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value : 0x0
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