72 lines
2.9 KiB
C
72 lines
2.9 KiB
C
/** @file
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Register names for PCH LPC/eSPI device
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_H_", "_PCH_LP_"
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Registers / bits names without _H_ or _LP_ apply for both H and LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_REGS_LPC_H_
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#define _PCH_REGS_LPC_H_
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//
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// PCI to LPC Bridge Registers (D31:F0)
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//
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#define PCI_DEVICE_NUMBER_PCH_LPC 31
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#define PCI_FUNCTION_NUMBER_PCH_LPC 0
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#define V_LPC_CFG_DID_EHL_LP 0x4B00
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typedef UINT8 PCH_STEPPING;
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#define PCH_A0 0x00
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#define PCH_STEPPING_MAX 0xFF
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#define R_LPC_CFG_IOD 0x80
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#define N_LPC_CFG_IOD_COMB 4
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#define V_LPC_CFG_IOD_COMB_3E8 7
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#define N_LPC_CFG_IOD_COMA 0
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#define V_LPC_CFG_IOD_COMA_3F8 0
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#define R_LPC_CFG_IOE 0x82
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#define B_LPC_CFG_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
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#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
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#define R_LPC_CFG_BC 0xDC ///< Bios Control
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#define R_PCH_LPC_IOD 0x80
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#define R_PCH_LPC_IOE 0x82
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#define R_PCH_LPC_GEN1_DEC 0x84
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#define B_PCH_LPC_GENX_DEC_IODRA 0x00FC0000
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#define B_PCH_LPC_GENX_DEC_IOBAR 0x0000FFFC
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#define B_PCH_LPC_GENX_DEC_EN 0x00000001
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#define R_PCH_ESPI_CS1GIR1 0xA4
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//
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// APM Registers
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//
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#define R_PCH_ESPI_PCBC 0xDC ///< Peripheral Channel BIOS Control
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#define B_PCH_ESPI_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap
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#endif
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