Maurice Ma acfe51f382 Sync up MTRR for MP before boot ... SBL might change MTRR to enable framebuffer cache. Current code only handles BSP MTRR programming, and it is necessary to sync up the MTRR programming for all APs as well. This patch added a function to sync up MTRRs for all APs. Please note, this MTRR sync up is a simplified version for SBL case since SBL will only add new MTRRs for GFX framebuffer. To do a full generic MTRRs sync up, it is required to flush cache, reload TLB, etc. And it will come with some performance impacts. Signed-off-by: Maurice Ma <maurice.ma@intel.com>		2021-11-05 11:09:16 -07:00
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Include	Build SMM HOBs for universal payload	2021-11-04 11:50:00 -07:00
IncludePrivate	SBL clean up to split core private data out	2021-11-04 10:49:49 -07:00
Library	Sync up MTRR for MP before boot	2021-11-05 11:09:16 -07:00
PcdData	Add missing header files in INF	2020-02-03 15:49:48 -08:00
Stage1A	Profile Max Used Heap size at runtime	2021-10-25 09:48:22 -07:00
Stage1B	Add UpdateMemoryInfo implementation for all open platforms	2021-10-29 07:49:55 -07:00
Stage2	Build SMM HOBs for universal payload	2021-11-04 11:50:00 -07:00
Tools	Add new Constant type for CFGDATA	2021-11-04 10:49:30 -07:00
BootloaderCorePkg.dec	SBL clean up to split core private data out	2021-11-04 10:49:49 -07:00
BootloaderCorePkg.dsc	Add PCD to let platform control the ACPI processor ID base	2021-10-25 16:43:20 -07:00
BootloaderCorePkg.fdf	Allow platform to override SOC or board specific inf files	2020-11-13 16:03:39 -08:00