335 lines
16 KiB
Python
335 lines
16 KiB
Python
## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2017-2019, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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import shutil
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import time
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sys.dont_write_bytecode = True
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sys.path.append (os.path.join('..', '..'))
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from BuildLoader import BaseBoard, STITCH_OPS, FLASH_REGION_TYPE
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from BuildLoader import HASH_USAGE
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class Board(BaseBoard):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_CFL'
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 1
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self.VERINFO_SVN = 1
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self.VERINFO_BUILD_DATE = time.strftime("%m/%d/%Y")
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self.LOWEST_SUPPORTED_FW_VER = ((self.VERINFO_PROJ_MAJOR_VER << 8) + self.VERINFO_PROJ_MINOR_VER)
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self.BOARD_NAME = 'cfl'
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self.BOARD_PKG_NAME = 'CoffeelakeBoardPkg'
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self.SILICON_PKG_NAME = 'CoffeelakePkg'
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self.PCI_EXPRESS_BASE = 0xE0000000
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self.PCI_IO_BASE = 0x00003000
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self.PCI_MEM32_BASE = 0x9F000000
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self.ACPI_PM_TIMER_BASE = 0x1808
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self._PCI_ENUM_DOWNGRADE_PMEM64 = 1
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self._PCI_ENUM_DOWNGRADE_MEM64 = 1
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self._PCI_ENUM_DOWNGRADE_BUS0 = 1
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self.PCI_MEM64_BASE = 0x4000000000
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self.FLASH_BASE_ADDRESS = 0xFE000000
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self.FLASH_BASE_SIZE = (self.FLASH_LAYOUT_START - self.FLASH_BASE_ADDRESS)
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self.HAVE_FIT_TABLE = 1
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self.HAVE_VBT_BIN = 1
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self.HAVE_VERIFIED_BOOT = 1
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self.HAVE_MEASURED_BOOT = 1
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self.HAVE_ACPI_TABLE = 1
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self.ENABLE_SPLASH = 1
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self.ENABLE_FRAMEBUFFER_INIT = 1
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self.HAVE_PSD_TABLE = 1
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self.ENABLE_GRUB_CONFIG = 1
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self.ENABLE_CSME_UPDATE = 0
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self.ENABLE_DMA_PROTECTION = 0
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self.ENABLE_SMM_REBASE = 2
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self.DEBUG_PORT_NUMBER = 0xFF
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# BIT0: Log buffer
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# BIT1: Serial port
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# BIT2: Platform debug port
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# BIT7: Platform console devices
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self.DEBUG_OUTPUT_DEVICE_MASK = 0x03
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# Input consoles
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# BIT0: Serial port
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# BIT1: USB Keyboard
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# BIT2: Platform debug port
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self.CONSOLE_IN_DEVICE_MASK = 0x00000001
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# Output consoles
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# BIT0: Serial port
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# BIT1: Framebuffer
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# BIT2: Platform debug port
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self.CONSOLE_OUT_DEVICE_MASK = 0x00000001
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# CSME update library is required to enable this option and will be available as part of CSME kit
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self.BUILD_CSME_UPDATE_DRIVER = 0
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# To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
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self.ENABLE_SOURCE_DEBUG = 0
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# If ENABLE_SOURCE_DEBUG is disabled, SKIP_STAGE1A_SOURCE_DEBUG will be ignored
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self.SKIP_STAGE1A_SOURCE_DEBUG = 0
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if self.HAVE_FIT_TABLE:
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self.FIT_ENTRY_MAX_NUM = 12
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self.STAGE1A_SIZE = 0x00010000
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if self.FSPDEBUG_MODE == 1:
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self.STAGE1B_SIZE = 0x00100000
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else:
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self.STAGE1B_SIZE = 0x000DB000
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self.STAGE2_SIZE = 0x00080000
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if self.ENABLE_SOURCE_DEBUG:
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self.STAGE1B_SIZE += 0x4000
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self.ENABLE_FWU = 1
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self.ENABLE_SMBIOS = 1
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# Verify required minimum FSP version
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self.MIN_FSP_REVISION = 0x07006550
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# Verify FSP image ID. Empty string means skipping verification
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self.FSP_IMAGE_ID = '$CFLFSP$'
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self.STAGE1B_XIP = 1
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# Stack settings to run FspMemoryInit
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self.FSP_M_STACK_TOP = 0xFEF3FF00
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self.STAGE2_FD_BASE = 0x01000000
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self.STAGE2_FD_SIZE = 0x000E0000
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self.STAGE1_STACK_SIZE = 0x00002000
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self.STAGE1_DATA_SIZE = 0x00014000
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self.PAYLOAD_EXE_BASE = 0x00B00000
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self.PAYLOAD_SIZE = 0x00029000
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if len(self._PAYLOAD_NAME.split(';')) > 1:
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self.UEFI_VARIABLE_SIZE = 0x00040000
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else:
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self.UEFI_VARIABLE_SIZE = 0x1000
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self.EPAYLOAD_SIZE = 0x00190000
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self.UCODE_SIZE = 0x00080000
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self.MRCDATA_SIZE = 0x00008000
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self.CFGDATA_SIZE = 0x00004000
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self.KEYHASH_SIZE = 0x00001000
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self.VARIABLE_SIZE = 0x00002000
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self.SBLRSVD_SIZE = 0x00001000
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self.FWUPDATE_SIZE = 0x00020000 if self.ENABLE_FWU else 0
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self.TOP_SWAP_SIZE = 0x020000
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self.REDUNDANT_SIZE = self.UCODE_SIZE + self.STAGE2_SIZE + self.STAGE1B_SIZE + \
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self.FWUPDATE_SIZE + self.CFGDATA_SIZE + self.KEYHASH_SIZE
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self.NON_VOLATILE_SIZE = 0x001000
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self.SLIMBOOTLOADER_SIZE = 0x800000
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self.NON_REDUNDANT_SIZE = self.SLIMBOOTLOADER_SIZE - \
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(self.TOP_SWAP_SIZE + self.REDUNDANT_SIZE) * 2 - \
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self.NON_VOLATILE_SIZE
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self.PLD_HEAP_SIZE = 0x04000000
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self.PLD_STACK_SIZE = 0x00020000
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self.PLD_RSVD_MEM_SIZE = 0x00500000
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# TBD: ACM/KM/BPM Size, as of Sep 2017
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# ACM size is fixed 100KB, KM size is fixed 0x400, BPM size is fixed 0x600
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self.KM_SIZE = 0x00000400
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self.BPM_SIZE = 0x00000600
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self.ACM_SIZE = 0x00008000 + self.KM_SIZE + self.BPM_SIZE
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# adjust ACM_SIZE to meet 128KB alignment (to align 100KB ACM size)
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if self.ACM_SIZE > 0:
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acm_top = self.FLASH_LAYOUT_START - self.STAGE1A_SIZE
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acm_btm = acm_top - self.ACM_SIZE
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acm_btm = (acm_btm & 0xFFFE0000)
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self.ACM_SIZE = acm_top - acm_btm
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self.CFGDATA_REGION_TYPE = FLASH_REGION_TYPE.BIOS
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self.SPI_IAS_REGION_TYPE = FLASH_REGION_TYPE.BIOS
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self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE + 0x4000
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self._CFGDATA_INT_FILE = ['CfgDataInt_Cfls.dlt', 'CfgDataInt_Cflh.dlt', 'CfgDataInt_Whl.dlt']
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self._CFGDATA_EXT_FILE = ['CfgDataExt_Upx.dlt']
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# If mulitple VBT table support is required, list them as:
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# {VbtImageId1 : VbtFileName1, VbtImageId2 : VbtFileName2, ...}
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# VbtImageId is ID to identify a VBT image. It is a UINT32 number to match
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# the ImageId field in the VBT container.
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# VbtFileName is the VBT file name. It needs to be located under platform
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# VbtBin folder.
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self._MULTI_VBT_FILE = {1:'Vbt.dat', 2:'VbtCflH.dat', 3:'VbtCflS.dat'}
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def GetPlatformDsc (self):
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debug_port_enable = False
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if (self.CONSOLE_OUT_DEVICE_MASK & 0x04) or (self.CONSOLE_IN_DEVICE_MASK & 0x04) or (self.DEBUG_OUTPUT_DEVICE_MASK & 0x04):
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debug_port_enable = True
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dsc = {}
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common_libs = [
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'LoaderLib|Platform/CommonBoardPkg/Library/LoaderLib/LoaderLib.inf',
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'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
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'PchSpiLib|Silicon/CommonSocPkg/Library/PchSpiLib/PchSpiLib.inf',
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'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
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'PchSbiAccessLib|Silicon/CommonSocPkg/Library/PchSbiAccessLib/PchSbiAccessLib.inf',
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'PchInfoLib|Silicon/$(SILICON_PKG_NAME)/Library/PchInfoLib/PchInfoLib.inf',
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'PchSerialIoLib|Silicon/$(SILICON_PKG_NAME)/Library/PchSerialIoLib/PchSerialIoLib.inf',
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'GpioLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioLib/GpioLib.inf',
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'IgdOpRegionLib|Silicon/$(SILICON_PKG_NAME)/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
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'BdatLib|Silicon/CommonSocPkg/Library/BdatLib/BdatLib.inf',
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'BootMediaLib|Silicon/$(SILICON_PKG_NAME)/Library/BootMediaLib/BootMediaLib.inf',
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'StageCommonLib|Silicon/$(SILICON_PKG_NAME)/Library/StageCommonLib/StageCommonLib.inf',
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'BootGuardLib|Silicon/$(SILICON_PKG_NAME)/Library/BootGuardLib/BootGuardLib.inf',
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'SgxLib|Silicon/$(SILICON_PKG_NAME)/Library/SgxLib/SgxLib.inf',
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'PsdLib|Silicon/$(SILICON_PKG_NAME)/Library/PsdLib/PsdLib.inf',
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'HeciLib|Silicon/CommonSocPkg/Library/HeciLib/HeciLib.inf',
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'MeChipsetLib|Silicon/CommonSocPkg/Library/MeChipsetLib/MeChipsetLib.inf',
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'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
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'VtdPmrLib|Silicon/CommonSocPkg/Library/VtdPmrLib/VtdPmrLib.inf'
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]
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if self.BUILD_CSME_UPDATE_DRIVER:
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common_libs.append ('MeFwUpdateLib|Silicon/$(SILICON_PKG_NAME)/Library/MeFwUpdateLib/MeFwUpdateLib.inf')
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if debug_port_enable:
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common_libs.append ('GpioDebugPortLib|Platform/CommonBoardPkg/Library/GpioDebugPortLib/GpioDebugPortLib.inf')
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common_libs.append ('MailboxDebugPortLib|Platform/CommonBoardPkg/Library/MailboxDebugPortLib/MailboxDebugPortLib.inf')
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common_libs.append ('DebugPortLib|Platform/$(BOARD_PKG_NAME)/Library/DebugPortLib/DebugPortLib.inf')
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dsc['LibraryClasses.%s' % self.BUILD_ARCH] = common_libs
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fixed_pcds = []
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if debug_port_enable:
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# Use GPIO_CNL_LP_GPP_H12 pin for example
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# Refer to GpioPinsCnlLp.h file to look up its GPIO pad value.
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# The GPIO pad value is 0x0407000C.
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gpio_pad = 0 # 0x0407000C for GPIO_CNL_LP_GPP_H12
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# IOSF SB access address for the GPIO DW0 register (DWORD)
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# Calculate the IOSF SB access address for GPIO DW0 register
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# - Get GPIO DW0 offset from SOC EDS datasheet. It is 0x9D0 for H12.
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# - Get GPIO community ID. It is community 1 for H12.
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# - Look up PID_GPIOCOM1 in file PchRegsPcr.h for PortId. It is 0x6D.
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# IOSF_MMIO = 0xFD000000 + (PortId<<16) + GpioOffset
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# If set to 0, gpio debug port will be disabled.
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iosf_mmio = 0 # 0xFD6D09D0 for GPIO_CNL_LP_GPP_H12
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fixed_pcds = [
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'gCommonBoardTokenSpaceGuid.PcdGpioDebugPortPinPad | 0x%08X' % gpio_pad,
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'gCommonBoardTokenSpaceGuid.PcdGpioDebugPortMmioBase | 0x%08X' % iosf_mmio
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]
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# Mailbox debug port, use GPI Interrupt Enable register as example
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# IOSF SB access address for the mailbox register (DWORD)
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# If set to 0, mailbox debug port will be disabled
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mailbox_mmio = 0 # 0xFD6E0120
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fixed_pcds.append (
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'gCommonBoardTokenSpaceGuid.PcdMailboxDebugPortMmioBase | 0x%08X' % mailbox_mmio,
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)
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if len(fixed_pcds) > 0:
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dsc['PcdsFixedAtBuild.%s' % self.BUILD_ARCH] = fixed_pcds
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return dsc
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def GetKeyHashList (self):
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# Define a set of new key used for different purposes
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# The key is either key id or public key PEM format or private key PEM format
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pub_key_list = [
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(
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# Key for verifying Config data blob
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HASH_USAGE['PUBKEY_CFG_DATA'],
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'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying firmware update
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HASH_USAGE['PUBKEY_FWU'],
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'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying container header
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HASH_USAGE['PUBKEY_CONT_DEF'],
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'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# key for veryfying OS image.
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HASH_USAGE['PUBKEY_OS'],
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'KEY_ID_OS1_PUBLIC' + '_' + self._RSA_SIGN_TYPE
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),
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]
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return pub_key_list
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def GetImageLayout (self):
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img_list = []
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acm_flag = 0 if self.ACM_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
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fwu_flag = 0 if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
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cfg_flag = 0 if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.BIOS else STITCH_OPS.MODE_FILE_IGNOR
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# output files need to have unique base name (excluding file extension)
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# output files ends with 'rom' extension will be copied over for final stitching
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img_list.extend ([
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('NON_VOLATILE.bin', [
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('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('NON_REDUNDANT.bin', [
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('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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('MRCDATA.bin' , '' , self.MRCDATA_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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('EPAYLOAD.bin', '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('UEFIVARIABLE.bin', '' , self.UEFI_VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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('PAYLOAD.bin' , 'Lz4' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('REDUNDANT_A.bin', [
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('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
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('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
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('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1B_A.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('REDUNDANT_B.bin', [
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('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
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('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
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('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1B_B.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('TOP_SWAP_A.bin', [
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('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('TOP_SWAP_B.bin', [
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('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
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('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('SlimBootloader.bin', [
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('NON_VOLATILE.bin' , '' , self.NON_VOLATILE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('NON_REDUNDANT.bin' , '' , self.NON_REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('REDUNDANT_B.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('REDUNDANT_A.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('TOP_SWAP_B.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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('TOP_SWAP_A.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
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]
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),
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])
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return img_list
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