419 lines
22 KiB
Python
419 lines
22 KiB
Python
## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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import time
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sys.dont_write_bytecode = True
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sys.path.append (os.path.join('..', '..'))
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from BuildLoader import BaseBoard, STITCH_OPS, FLASH_REGION_TYPE, HASH_USAGE
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from BuildLoader import IPP_CRYPTO_OPTIMIZATION_MASK, IPP_CRYPTO_ALG_MASK, HASH_TYPE_VALUE
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class Board(BaseBoard):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_EHLK '
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# VERINFO_PROJ_MAJOR_VER: 1 PV Quality release
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# VERINFO_PROJ_MINOR_VER: 0: PV 1: MR1 2: MR2 etc.
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 3
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self.VERINFO_SVN = 1
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self.VERINFO_BUILD_DATE = time.strftime("%m/%d/%Y")
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self.LOWEST_SUPPORTED_FW_VER = ((self.VERINFO_PROJ_MAJOR_VER << 8) + self.VERINFO_PROJ_MINOR_VER)
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self.BOARD_NAME = 'ehl'
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self.BOARD_PKG_NAME = 'ElkhartlakeBoardPkg'
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self.SILICON_PKG_NAME = 'ElkhartlakePkg'
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self.PCI_EXPRESS_BASE = 0xC0000000
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self.PCI_IO_BASE = 0x00002000
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self.PCI_MEM32_BASE = 0x80000000
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self.ACPI_PM_TIMER_BASE = 0x1808
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self.ACPI_PROCESSOR_ID_BASE = 0
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self.FLASH_BASE_ADDRESS = 0xFF000000
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self.FLASH_BASE_SIZE = (self.FLASH_LAYOUT_START - self.FLASH_BASE_ADDRESS)
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self.HAVE_FIT_TABLE = 1
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self.HAVE_FSP_BIN = 1
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self.HAVE_VBT_BIN = 1 if self.HAVE_FSP_BIN != 0 else 0
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self.HAVE_VERIFIED_BOOT = 1
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self.HAVE_MEASURED_BOOT = 1
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self.HAVE_ACPI_TABLE = 1
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self.HAVE_PSD_TABLE = 1
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self.ENABLE_VTD = 1
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self.ENABLE_SPLASH = 1
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# 0: Disable 1: Enable 2: Auto (disable for UEFI payload, enable for others)
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self.ENABLE_SMM_REBASE = 2
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self.ENABLE_FRAMEBUFFER_INIT = 1
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self.SIIPFW_SIZE = 0x1000
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self.ENABLE_TCC = 0
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# TSN manual configuration- If enabled, user will be able to have more refined control over TSN configuration via
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# PseTsnIpConfig, TsnConfig and TsnMacAddr binaries
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self.ENABLE_TSN = 0
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if self.ENABLE_TCC:
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self.TCC_CCFG_SIZE = 0x00001000
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self.TCC_CRL_SIZE = 0x00008000
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self.TCC_STREAM_SIZE = 0x00005000
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self.SIIPFW_SIZE += self.TCC_CCFG_SIZE + self.TCC_CRL_SIZE + self.TCC_STREAM_SIZE
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self.ENABLE_PRE_OS_CHECKER = 1
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if self.ENABLE_PRE_OS_CHECKER:
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self.POSC_SIZE = 0x00028000
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self.SIIPFW_SIZE += self.POSC_SIZE
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bins = os.path.join(os.path.dirname(os.path.realpath(__file__)), 'Binaries')
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if os.path.exists(os.path.join(bins, 'PseFw.bin')):
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self.ENABLE_PSEFW_LOADING = 1
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else:
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self.ENABLE_PSEFW_LOADING = 0
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if self.ENABLE_PSEFW_LOADING:
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self.PSEF_SIZE = 0x00030000
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self.SIIPFW_SIZE += self.PSEF_SIZE
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if self.ENABLE_TSN:
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self.TSNC_SIZE = 0x00001000
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self.TMAC_SIZE = 0x00001000
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self.PSE_TSIP_SIZE = 0x00001000 if self.ENABLE_PSEFW_LOADING == 1 else 0
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self.SIIPFW_SIZE += self.TSNC_SIZE + self.TMAC_SIZE + self.PSE_TSIP_SIZE
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if self.HAVE_FIT_TABLE:
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self.FIT_ENTRY_MAX_NUM = 10
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# RSA2048 or RSA3072
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self._RSA_SIGN_TYPE = 'RSA3072'
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# 'SHA2_256' or 'SHA2_384'
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self._SIGN_HASH = 'SHA2_384'
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# 0x01 for SHA2_256 or 0x02 for SHA2_384
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self.SIGN_HASH_TYPE = HASH_TYPE_VALUE[self._SIGN_HASH]
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# 0x0010 for SM3_256 | 0x0008 for SHA2_512 | 0x0004 for SHA2_384 | 0x0002 for SHA2_256 | 0x0001 for SHA1
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self.IPP_HASH_LIB_SUPPORTED_MASK = IPP_CRYPTO_ALG_MASK['SHA2_384'] | IPP_CRYPTO_ALG_MASK['SHA2_256']
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# G9 for 384 | W7 Opt for SHA384| Ni Opt for SHA256| V8 Opt for SHA256
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self.ENABLE_CRYPTO_SHA_OPT = IPP_CRYPTO_OPTIMIZATION_MASK['SHA256_NI'] | IPP_CRYPTO_OPTIMIZATION_MASK['SHA384_W7']
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# Key configuration
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self._MASTER_PRIVATE_KEY = 'KEY_ID_MASTER' + '_' + self._RSA_SIGN_TYPE
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self._CFGDATA_PRIVATE_KEY = 'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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self._CONTAINER_PRIVATE_KEY = 'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
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self.DEBUG_PORT_NUMBER = 0x2
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self.STAGE1A_SIZE = 0x00028000
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self.STAGE1B_SIZE = 0x00120000
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self.STAGE2_SIZE = 0x00091000
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self.ENABLE_FWU = 1
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self.ENABLE_CSME_UPDATE = 1
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self.ENABLE_SMBIOS = 1
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# CSME update library is required to enable this option and will be available as part of CSME kit
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self.BUILD_CSME_UPDATE_DRIVER = 0
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self.STAGE1B_XIP = 1
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self.STAGE2_FD_BASE = 0x01000000
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self.STAGE2_FD_SIZE = 0x00100000
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self.STAGE1_STACK_SIZE = 0x00020000
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self.STAGE1_DATA_SIZE = 0x00015000
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# if PAYLOAD_LOAD_HIGH is 1, PAYLOAD_EXE_BASE will be ignored
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self.PAYLOAD_LOAD_HIGH = 1
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self.PAYLOAD_EXE_BASE = 0x00B00000
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self.PAYLOAD_SIZE = 0x00020000
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self.EPAYLOAD_SIZE = 0x00162000
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self.UCODE_SIZE = 0x00010000 if self.HAVE_FSP_BIN != 0 else 0
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self.MRCDATA_SIZE = 0x00008000
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self.CFGDATA_SIZE = 0x00004000
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self.KEYHASH_SIZE = 0x00001000
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self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE + 0x1000
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self.VARIABLE_SIZE = 0x00002000
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if len(self._PAYLOAD_NAME.split(';')) > 1:
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self.UEFI_VARIABLE_SIZE = 0x00040000
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else:
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self.UEFI_VARIABLE_SIZE = 0x00001000
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self.SBLRSVD_SIZE = 0x00001000
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self.FWUPDATE_SIZE = 0x0001B000 if self.ENABLE_FWU else 0
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self.TOP_SWAP_SIZE = 0x080000
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self.REDUNDANT_SIZE = 0x360000
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self.NON_VOLATILE_SIZE = 0x001000
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self.SLIMBOOTLOADER_SIZE = 0xD00000
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self.NON_REDUNDANT_SIZE = self.SLIMBOOTLOADER_SIZE - \
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(self.TOP_SWAP_SIZE + self.REDUNDANT_SIZE) * 2 - \
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self.NON_VOLATILE_SIZE
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# TBD: ACM/KM/BPM Size, as of Sep 2017
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# ACM size is fixed 100KB, KM size is fixed 0x400, BPM size is fixed 0x600
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self.KM_SIZE = 0x00000400
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self.BPM_SIZE = 0x00000600
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self.ACM_SIZE = 0x00020000 + self.KM_SIZE + self.BPM_SIZE
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# adjust ACM_SIZE to meet 128KB alignment (to align 100KB ACM size)
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if self.ACM_SIZE > 0:
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acm_top = self.FLASH_LAYOUT_START - self.STAGE1A_SIZE
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acm_btm = acm_top - self.ACM_SIZE
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acm_btm = (acm_btm & 0xFFFE0000)
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self.ACM_SIZE = acm_top - acm_btm
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self.CFGDATA_REGION_TYPE = FLASH_REGION_TYPE.BIOS
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self.SPI_IAS_REGION_TYPE = FLASH_REGION_TYPE.BIOS
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self.SPI_IAS1_SIZE = 0x0
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self.SPI_IAS2_SIZE = 0x0
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self.PLD_HEAP_SIZE = 0x04000000
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self.PLD_STACK_SIZE = 0x00020000
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self.PLD_RSVD_MEM_SIZE = 0x00500000
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self.LOADER_RSVD_MEM_SIZE = 0x500000
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# _CFGDATA_INT_FILE - Internal cfg data is generally used for internal boards like MRBs, RVPs etc.
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# _CFGDATA_EXT_FILE - External cfg data is for the customer boards to populate new data on top of the internal defaults.
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# Cfg data dlt files for internal boards could also put into external cfg data if want to update cfg data for these platforms
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# for test purpose. Based on the platform id, relevant data is populated for each platform.
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self._generated_cfg_file_prefix = 'Autogen_'
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self._CFGDATA_INT_FILE = []
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self._CFGDATA_EXT_FILE = [self._generated_cfg_file_prefix + 'CfgData_Int_IotgRvp1.dlt', self._generated_cfg_file_prefix + 'CfgData_Ext_IotgCrb.dlt', self._generated_cfg_file_prefix + 'CfgData_Ext_Up6000.dlt']
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def PlatformBuildHook (self, build, phase):
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if phase == 'pre-build:before':
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# create build folder if not exist
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if not os.path.exists(build._fv_dir):
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os.makedirs(build._fv_dir)
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# Generate the dlt files based on feature
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brd_cfg_src_dir = os.path.join(os.environ['PLT_SOURCE'], 'Platform', self.BOARD_PKG_NAME, 'CfgData')
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for dlt_file in self._CFGDATA_EXT_FILE:
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cfg_dlt_file = os.path.join(brd_cfg_src_dir, dlt_file[len (self._generated_cfg_file_prefix):])
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lines = open (cfg_dlt_file).read()
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# Enable TCC in dlt file
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if self.ENABLE_TCC:
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lines += open (os.path.join(brd_cfg_src_dir, 'CfgData_Tcc_Feature.dlt')).read()
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# Write to generated final dlt file
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output_cfg_dlt_file = os.path.join(build._fv_dir, dlt_file)
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open(output_cfg_dlt_file, 'w').write(lines)
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def GetPlatformDsc (self):
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dsc = {}
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# These libraries will be added into the DSC files
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common_libs = [
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'LoaderLib|Platform/CommonBoardPkg/Library/LoaderLib/LoaderLib.inf',
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'PchInfoLib|Silicon/$(SILICON_PKG_NAME)/Library/PchInfoLib/PchInfoLib.inf',
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'PchSbiAccessLib|Silicon/CommonSocPkg/Library/PchSbiAccessLib/PchSbiAccessLib.inf',
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'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
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'TccLib|Silicon/CommonSocPkg/Library/TccLib/TccLib.inf',
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'GpioLib|Silicon/CommonSocPkg/Library/GpioLib/GpioLib.inf',
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'GpioSiLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioSiLib/GpioSiLib.inf',
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'PchSpiLib|Silicon/CommonSocPkg/Library/PchSpiLib/PchSpiLib.inf',
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'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
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'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VTdLib/VTdLib.inf',
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'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
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'IgdOpRegionLib|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
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'BootGuardLib|Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardLibCBnT.inf',
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'BdatLib|Silicon/CommonSocPkg/Library/BdatLib/BdatLib.inf',
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'PchSciLib|Silicon/$(SILICON_PKG_NAME)/Library/PchSciLib/PchSciLib.inf',
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'SmbusLib|Silicon/CommonSocPkg/Library/SmbusLib/SmbusLib.inf',
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'PsdLib|Silicon/$(SILICON_PKG_NAME)/Library/PsdLib/PsdLib.inf',
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'HeciInitLib|Silicon/$(SILICON_PKG_NAME)/Library/HeciInitLib/HeciInitLib.inf',
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'MeExtMeasurementLib|Silicon/$(SILICON_PKG_NAME)/Library/MeExtMeasurementLib/MeExtMeasurementLib.inf'
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]
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if self.BUILD_CSME_UPDATE_DRIVER:
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common_libs.append ('MeFwUpdateLib|Silicon/$(SILICON_PKG_NAME)/Library/MeFwUpdateLib/MeFwUpdateLib.inf')
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dsc['LibraryClasses.%s' % self.BUILD_ARCH] = common_libs
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return dsc
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def GetKeyHashList (self):
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# Define a set of new key used for different purposes
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# The key is either key id or public key PEM format or private key PEM format
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pub_key_list = [
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(
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# Key for verifying Config data blob
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HASH_USAGE['PUBKEY_CFG_DATA'],
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'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying firmware update
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HASH_USAGE['PUBKEY_FWU'],
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'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying container header
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HASH_USAGE['PUBKEY_CONT_DEF'],
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'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Use RSA2048 key for verifying OS image signed with RSA2048
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HASH_USAGE['PUBKEY_OS'],
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'KEY_ID_OS1_PUBLIC_RSA2048'
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),
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(
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# Use RSA3072 key for verifying OS image signed with RSA3072
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HASH_USAGE['PUBKEY_OS'],
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'KEY_ID_OS1_PUBLIC_RSA3072'
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),
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]
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return pub_key_list
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def GetContainerList (self):
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container_list = []
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container_list_auth_type = self._RSA_SIGN_TYPE + '_'+ self._SIGNING_SCHEME[4:] + '_' + self._SIGN_HASH
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container_list.append (
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# Name | Image File | CompressAlg | AuthType | Key File | Region Align | Region Size | Svn Info
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# ===============================================================================================================================================================
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('IPFW', 'SIIPFW.bin', '', container_list_auth_type, 'KEY_ID_CONTAINER'+'_'+self._RSA_SIGN_TYPE, 0, 0 , 0), # Container Header
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)
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bins = os.path.join(os.path.dirname(os.path.realpath(__file__)), 'Binaries')
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CompFilePreOsChecker='PreOsChecker.bin' if os.path.exists(os.path.join(bins, 'PreOsChecker.bin')) else ''
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CompFilePseFw='PseFw.bin' if os.path.exists(os.path.join(bins, 'PseFw.bin')) else ''
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CompFilePseTsnIpConfig='PseTsnIpConfig.bin' if os.path.exists(os.path.join(bins, 'PseTsnIpConfig.bin')) else ''
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CompFileTsnConfig='TsnConfig.bin' if os.path.exists(os.path.join(bins, 'TsnConfig.bin')) else ''
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CompFileTsnMacAddr='TsnMacAddr.bin' if os.path.exists(os.path.join(bins, 'TsnMacAddr.bin')) else ''
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CompFileCrlFw='crl.bin' if os.path.exists(os.path.join(bins, 'crl.bin')) else ''
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if self.ENABLE_TCC:
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container_list.append (
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('TCCC', '', 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TCC_CCFG_SIZE, 0), # TCC Cache Config
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)
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container_list.append (
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('TCCM', CompFileCrlFw, 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TCC_CRL_SIZE, 0), # TCC CRL
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)
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container_list.append (
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('TCCT', '', 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TCC_STREAM_SIZE,0), # TCC Stream Config
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)
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if self.ENABLE_PRE_OS_CHECKER:
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container_list.append (
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('POSC',CompFilePreOsChecker, '', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.POSC_SIZE, 0), # Pre-OS Checker
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)
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if self.ENABLE_PSEFW_LOADING:
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container_list.append (
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('PSEF',CompFilePseFw, 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.PSEF_SIZE, 0), # OSE FW
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)
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if self.ENABLE_TSN:
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container_list.append (
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('TSNC',CompFileTsnConfig, 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TSNC_SIZE, 0), # TSN Config
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)
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container_list.append (
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('TMAC',CompFileTsnMacAddr, 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.TMAC_SIZE, 0), # TSN MAC Address
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)
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if self.ENABLE_PSEFW_LOADING:
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container_list.append (
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('TSIP',CompFilePseTsnIpConfig, 'Lz4', container_list_auth_type, 'KEY_ID_CONTAINER_COMP'+'_'+self._RSA_SIGN_TYPE, 0, self.PSE_TSIP_SIZE, 0), # PSE TSN IP
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)
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return [container_list]
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def GetOutputImages (self):
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# define extra images that will be copied to output folder
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img_list = ['SlimBootloader.txt',
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'FlashMap.txt',
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'CfgDataStitch.py',
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'CfgDataDef.yaml']
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return img_list
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def GetImageLayout (self):
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acm_flag = 0 if self.ACM_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
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ias1_flag = 0 if self.SPI_IAS1_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
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ias2_flag = 0 if self.SPI_IAS2_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
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fwu_flag = 0 if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
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if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.BIOS:
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cfg_flag = 0
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else:
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cfg_flag = STITCH_OPS.MODE_FILE_IGNOR
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img_list = []
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if len(self._CFGDATA_EXT_FILE) > 0 and self.CFGDATA_REGION_TYPE == FLASH_REGION_TYPE.PLATFORMDATA:
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img_list.extend ([
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('CfgDataPdr.bin', [
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('CFGDATA.bin', '', self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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])
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# output files need to have unique base name (excluding file extension)
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# output files ends with 'rom' extension will be copied over for final stitching
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ucode_flag = 0 if self.HAVE_FSP_BIN else STITCH_OPS.MODE_FILE_IGNOR
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img_list.extend ([
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('NON_VOLATILE.bin', [
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('SBLRSVD.bin', '' , self.SBLRSVD_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
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]
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),
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('NON_REDUNDANT.bin', [
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('SIIPFW.bin' , '' , self.SIIPFW_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
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('SPI_IAS2.bin' , '' , self.SPI_IAS2_SIZE, STITCH_OPS.MODE_FILE_PAD | ias2_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('SPI_IAS1.bin' , '' , self.SPI_IAS1_SIZE, STITCH_OPS.MODE_FILE_PAD | ias1_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('VARIABLE.bin' , '' , self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
('MRCDATA.bin' , '' , self.MRCDATA_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
('EPAYLOAD.bin' , '' , self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('UEFIVARIABLE.bin', '' , self.UEFI_VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
('PAYLOAD.bin' , 'Lzma' , self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('REDUNDANT_A.bin', [
|
|
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD | ucode_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1B_A.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('REDUNDANT_B.bin', [
|
|
('UCODE.bin' , '' , self.UCODE_SIZE, STITCH_OPS.MODE_FILE_PAD | ucode_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE2.fd' , 'Lz4' , self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('FWUPDATE.bin' , 'Lzma' , self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('CFGDATA.bin' , '' , self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD | cfg_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('KEYHASH.bin' , '' , self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1B_B.fd' , '' , self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('TOP_SWAP_A.bin', [
|
|
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1A_A.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('TOP_SWAP_B.bin', [
|
|
('ACM.bin' , '' , self.ACM_SIZE, STITCH_OPS.MODE_FILE_NOP | acm_flag, STITCH_OPS.MODE_POS_TAIL),
|
|
('STAGE1A_B.fd' , '' , self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL),
|
|
]
|
|
),
|
|
('SlimBootloader.bin', [
|
|
('NON_VOLATILE.bin' , '' , self.NON_VOLATILE_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('NON_REDUNDANT.bin' , '' , self.NON_REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('REDUNDANT_B.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('REDUNDANT_A.bin' , '' , self.REDUNDANT_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('TOP_SWAP_B.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
('TOP_SWAP_A.bin' , '' , self.TOP_SWAP_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_HEAD),
|
|
]
|
|
),
|
|
])
|
|
|
|
return img_list
|