542 lines
26 KiB
YAML
542 lines
26 KiB
YAML
## @file
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#
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# Slim Bootloader CFGDATA Option File.
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#
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# Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.<BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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- $ACTION :
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page : SIL
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- SILICON_CFG_DATA :
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- !expand { CFGHDR_TMPL : [ SILICON_CFG_DATA, 0x200, 0, 0 ] }
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- InterruptRemappingSupport :
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name : InterruptRemappingSupport
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type : Combo
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option : $EN_DIS
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help : >
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InterruptRemappingSupport
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length : 0x01
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value : 0x1
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- PchTsnEnable :
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name : Enable PCH TSN
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type : Combo
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option : $EN_DIS
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help : >
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Enable/disable TSN on the PCH.
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length : 0x01
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value : 0x0
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- PchTsnLinkSpeed :
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name : TSN Link Speed
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type : Combo
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option : 0: Reserved, 1: Reserved, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps
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help : >
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Set TSN Link Speed. Only applicable for ADLN
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length : 0x01
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value : 0x03
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- PchTsnMultiVcEnable :
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name : Enable TSN Multi-VC
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type : Combo
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option : $EN_DIS
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help : >
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Enable/disable Multi Virtual Channels(VC) in TSN.
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length : 0x01
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value : 0x0
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- EnableItbm :
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condition : $(COND_S0IX_DIS)
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name : Intel Turbo Boost Max Technology 3.0
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type : Combo
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option : $EN_DIS
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help : >
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Intel Turbo Boost Max Technology 3.0. 0- Disabled; <b>1- Enabled</b>
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length : 0x01
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value : 0x00
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- AcSplitLock :
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name : AC Split Lock
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type : Combo
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option : $EN_DIS
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help : >
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Enable/Disable #AC check on split lock. <b>0- Disable</b>; 1- Enable.
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length : 0x1
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value : 0x0
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- PsfTccEnable :
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name : PSF Tcc
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type : Combo
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option : $EN_DIS
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help : >
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Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable some psf power management features, 0- Disable, 1- Enable
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length : 0x01
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value : 0x0
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- PchDmiAspmCtrl :
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name : Pch Dmi Aspm Ctrl
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type : Combo
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option : 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
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help : >
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ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
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length : 0x01
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value : 0x02
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- PchLegacyIoLowLatency :
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name : PCH Legacy IO Low Latency Enable
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type : Combo
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option : $EN_DIS
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help : >
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Set to enable low latency of legacy IO. <b>0- Disable</b>, 1- Enable
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length : 0x01
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value : 0x0
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- RenderStandby :
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name : Enable/Disable IGFX RenderStandby
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type : Combo
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option : $EN_DIS
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help : >
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Enable(Default)- Enable IGFX RenderStandby, Disable- Disable IGFX RenderStandby
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length : 0x01
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value : 0x1
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- PmSupport :
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name : Enable/Disable IGFX PmSupport
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type : Combo
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option : $EN_DIS
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help : >
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Enable(Default)- Enable IGFX PmSupport, Disable- Disable IGFX PmSupport
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length : 0x01
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value : 0x1
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- CpuPcieClockGating :
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name : CPU PCIe RootPort Clock Gating
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type : Combo
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option : $EN_DIS
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help : >
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Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0- Disable; 1- Enable.
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length : 0x01
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value : 0x1
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- CpuPciePowerGating :
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name : CPU PCIe RootPort Power Gating
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type : Combo
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option : $EN_DIS
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help : >
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Describes whether the PCI Express Power Gating for each root port is enabled by platform modules. 0- Disable; 1- Enable.
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length : 0x01
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value : 0x1
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- CpuPcieRpAspm :
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name : PCIE RP Aspm
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type : EditNum, HEX, (0x00,0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
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help : >
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The ASPM configuration of the root port (see- CPU_PCIE_ASPM_CONTROL). Default is CpuPcieAspmAutoConfig.
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length : 0x4
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value : {0x3, 0x2, 0x2, 0x0}
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- CpuPcieRpL1Substates :
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name : PCIE RP L1 Substates
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type : EditNum, HEX, (0x00,0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
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help : >
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The L1 Substates configuration of the root port (see- CPU_PCIE_L1SUBSTATES_CONTROL). Default is CpuPcieL1SubstatesL1_1_2.
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length : 0x4
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value : {0x2, 0x2, 0x2, 0x2}
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- CpuPcieRpPtmEnabled :
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name : PTM for PCIE RP Mask
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type : EditNum, HEX, (0x00,0x00FFFFFF)
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help : >
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Enable/disable Precision Time Measurement for PCIE Root Ports. 0- disable, 1- enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.
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length : 0x04
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value : { 0x01, 0x01, 0x01, 0x01 }
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- CpuPcieRpVcEnabled :
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name : VC for PCIE RP Mask
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type : EditNum, HEX, (0x00,0x00FFFFFF)
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help : >
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Enable/disable Virtual Channel for PCIE Root Ports. 0- disable, 1- enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.
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length : 0x04
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value : { 0x01, 0x01, 0x01, 0x01 }
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- CpuPcieRpMultiVcEnabled :
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name : Multi-VC for PCIE RP Mask
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type : EditNum, HEX, (0x00,0x00FFFFFF)
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help : >
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Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0- disable, 1- enable. One bit for each port, bit0 for port1, bit1 for port2, and so on.
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length : 0x04
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value : { 0x0, 0x0, 0x0, 0x0 }
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- EnableTimedGpio0 :
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condition : $(COND_S0IX_DIS)
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name : Timed GPIO 0
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type : Combo
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option : $EN_DIS
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help : >
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Enable/disable Timed GPIO0 0- Disable; 1- Enable.
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length : 0x01
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value : 0x0
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- EnableTimedGpio1 :
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condition : $(COND_S0IX_DIS)
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name : Timed GPIO 1
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type : Combo
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option : $EN_DIS
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help : >
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Enable/disable Timed GPIO1 0- Disable; 1- Enable.
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length : 0x01
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value : 0x0
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- SataEnable :
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name : Enable SATA
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type : Combo
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option : 0x1:Enabled, 0x0:Disabled
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help : >
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Enable/disable SATA controller.
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length : 0x0001
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value : 0x01
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- SataMode :
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name : SATA Mode
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type : Combo
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option : 0x0:AHCI, 0x1:RAID
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help : >
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Select SATA controller working mode.
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length : 0x0001
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value : 0x00
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- SataPwrOptEnable :
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name : PCH Sata Pwr Opt Enable
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type : Combo
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option : 0x1:Enabled, 0x0:Disabled
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help : >
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SATA Power Optimizer on PCH side.
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length : 0x0001
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value : 0x01
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- SataLedEnable :
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name : SATA LED
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type : Combo
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option : 0x1:Enabled, 0x0:Disabled
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help : >
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SATA LED indicating SATA controller activity. 0- disable, 1- enable
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length : 0x0001
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value : 0x01
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- SataPortsEnable :
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name : Enable SATA ports
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFFFF)
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help : >
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Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
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length : 0x0008
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value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
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- SataPortsDevSlp :
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name : Enable SATA DEVSLP Feature
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFFFF)
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help : >
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Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on.
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length : 0x0008
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value : {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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- SataPortsDmVal :
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name : Enable SATA Port DmVal
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFFFF)
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help : >
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DITO multiplier. Default is 15.
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length : 0x0008
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value : {0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF}
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- SataPortsDitoVal :
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name : Enable SATA Port DmVal
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type : Table
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struct : UINT16
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option : 0:2:HEX, 1:2:HEX, 2:2:HEX, 3:2:HEX, 4:2:HEX, 5:2:HEX, 6:2:HEX, 7:2:HEX
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help : >
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DEVSLP Idle Timeout (DITO), Default is 625.
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length : 0x0010
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value : {0:0W,0x271,0x271,0x271,0x271,0x271,0x271,0x271,0x271}
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- PortUsb20Enable :
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name : Enable USB2 ports
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
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help : >
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Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
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length : 0x0010
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value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
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- PortUsb30Enable :
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name : Enable USB3 ports
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX
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help : >
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Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
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length : 0x000A
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value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
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- Usb2OverCurrentPin :
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name : USB2 Port Over Current Pin
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
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help : >
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Describe the specific over current pin number of USB 2.0 Port N.
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length : 0x0010
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value : {0xFF, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0x07, 0x00, 0xFF, 0x07, 0x00, 0x00, 0x00, 0x6, 0x07, 0x07}
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- Usb3OverCurrentPin :
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name : USB3 Port Over Current Pin
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX
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help : >
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Describe the specific over current pin number of USB 3.0 Port N.
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length : 0x000A
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value : {0xFF, 0xFF, 0x00, 0x00, 0x07, 0x07, 0xFF, 0xFF, 0x00, 0x00}
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- Usb2PhyPetxiset :
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name : USB Per Port HS Preemphasis Bias
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
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help : >
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USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
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length : 0x0010
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value : {0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00}
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- Usb2PhyPredeemp :
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name : USB Per Port HS Transmitter Emphasis
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
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help : >
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USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
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length : 0x0010
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value : {0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}
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- Usb2PhyTxiset :
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name : USB Per Port HS Transmitter Bias
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
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help : >
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USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
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length : 0x0010
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value : {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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- Usb2PhyPehalfbit :
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name : USB Per Port Half Bit Pre-emphasis
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
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help : >
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USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port.
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length : 0x0010
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value : {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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- SerialIoUartMode :
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name : UARTn Device Mode
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFF)
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help : >
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Selects Uart operation mode. N represents controller index- Uart0, Uart1, ... Available modes- 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit
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length : 0x0007
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value : {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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- SerialIoUartPowerGating :
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name : Power Gating mode for each Serial IO UART that works in COM mode
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFF)
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help : >
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Set Power Gating. 0- Disabled, 1- Enabled, 2- Auto
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length : 0x0007
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value : {0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00}
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- SerialIoUartDmaEnable :
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name : Enable Dma for each Serial IO UART that supports it
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFF)
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help : >
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Set DMA/PIO mode. 0- Disabled, 1- Enabled
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length : 0x0007
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value : {0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00}
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- SerialIoUartAutoFlow :
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name : Enables UART hardware flow control, CTS and RTS lines
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFF)
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help : >
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Enables UART hardware flow control, CTS and RTS lines.
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length : 0x0007
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value : {0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
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- SerialIoSpiMode :
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name : SPIn Device Mode
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFF)
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help : >
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Selects SPI operation mode. N represents controller index- SPI0, SPI1, ... Available modes- 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
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length : 0x0007
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value : {0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}
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- SerialIoSpiCsPolarity :
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name : SPI<N> Chip Select Polarity
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type : Table
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option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX
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help : >
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Sets polarity for each chip Select. Available options- 0:SerialIoSpiCsActiveLow, 1:SerialIoSpiCsActiveHigh
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length : 0x000E
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value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
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- SerialIoI2cMode :
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name : I2Cn Device Mode
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFFFFFFFF)
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help : >
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Selects I2c operation mode. N represents controller index- I2c0, I2c1, ... Available modes- 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
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length : 0x0008
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value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00}
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- PchSerialIoI2cPadsTermination :
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name : PCH SerialIo I2C Pads Termination
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFFFF)
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help : >
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0x0- Hardware default, 0x1- None, 0x13- 1kOhm weak pull-up, 0x15- 5kOhm weak pull-up, 0x19- 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
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length : 0x0008
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value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
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- CpuUsb3OverCurrentPin :
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name : CPU USB3 Port Over Current Pin
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type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
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help : >
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Describe the specific over current pin number of USBC Port N.
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length : 0x0008
|
|
value : {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}
|
|
- PchUfsEnable :
|
|
name : Enable PCH UFS
|
|
type : EditNum, HEX, (0x0, 0x1)
|
|
help : >
|
|
Enable/Disable UFS controllers 1 and 2. 0- Disable; 1- Enable.
|
|
length : 0x02
|
|
value : {0x00, 0x00}
|
|
- PchIshI2cEnable :
|
|
condition : $(COND_S0IX_DIS)
|
|
name : Enable PCH ISH I2C pins assigned
|
|
type : EditNum, HEX, (0x0, 0xFFFFFF)
|
|
help : >
|
|
Set if ISH I2C native pins are to be enabled by BIOS. 0- Disable; 1- Enable.
|
|
length : 0x0003
|
|
value : {0x00, 0x00, 0x00}
|
|
- PchIshGpEnable :
|
|
condition : $(COND_S0IX_DIS)
|
|
name : Enable PCH ISH GP pins assigned
|
|
type : EditNum, HEX, (0x0, 0xFFFFFFFFFFFFFFFF)
|
|
help : >
|
|
Set if ISH GP native pins are to be enabled by BIOS. 0- Disable; 1- Enable.
|
|
length : 0x0008
|
|
value : {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
|
|
- PcieRpMaxPayload :
|
|
name : PCIE RP Max Payload
|
|
type : Table
|
|
option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
|
|
help : >
|
|
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
|
|
length : 0x001C
|
|
value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
|
|
- PcieRpL1Substates :
|
|
name : PCIE RP L1 Substates
|
|
type : Table
|
|
option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
|
|
help : >
|
|
The L1 Substates configuration of the root port (see- PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2.
|
|
length : 0x001C
|
|
value : {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
|
|
- PcieRpLtrEnable :
|
|
name : PCIE RP Ltr Enable
|
|
type : Table
|
|
option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
|
|
help : >
|
|
Latency Tolerance Reporting Mechanism.
|
|
length : 0x001C
|
|
value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
|
|
- PcieRpClkReqDetect :
|
|
name : Enable PCIE RP Clk Req Detect
|
|
type : Table
|
|
option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
|
|
help : >
|
|
Probe CLKREQ# signal before enabling CLKREQ# based power management.
|
|
length : 0x001C
|
|
value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
|
|
- PcieRpAdvancedErrorReporting :
|
|
name : PCIE RP Advanced Error Report
|
|
type : Table
|
|
option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
|
|
help : >
|
|
Indicate whether the Advanced Error Reporting is enabled.
|
|
length : 0x001C
|
|
value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
|
|
- PcieRpAspm :
|
|
name : PCIE RP Aspm
|
|
type : EditNum, HEX, (0x00,0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
|
|
help : >
|
|
The ASPM configuration of the root port (see- PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig.
|
|
length : 0x001C
|
|
value : {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}
|
|
- PciePtm :
|
|
name : PCIe PTM enable/disable
|
|
type : EditNum, HEX, (0x00,0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
|
|
help : >
|
|
Enable/disable Precision Time Measurement for PCIE Root Ports.
|
|
length : 0x001C
|
|
value : {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01}
|
|
- PcieRpPcieSpeed :
|
|
name : PCIE RP Pcie Speed
|
|
type : Table
|
|
option : 0:1:HEX, 1:1:HEX, 2:1:HEX, 3:1:HEX, 4:1:HEX, 5:1:HEX, 6:1:HEX, 7:1:HEX, 8:1:HEX, 9:1:HEX, A:1:HEX, B:1:HEX, C:1:HEX, D:1:HEX, E:1:HEX, F:1:HEX
|
|
help : >
|
|
Determines each PCIE Port speed capability. 0- Auto; 1- Gen1; 2- Gen2; 3- Gen3 (see- PCIE_SPEED).
|
|
length : 0x001C
|
|
value : {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
|
|
- PtmEnabled :
|
|
name : Enable/Disable PTM
|
|
type : EditNum, HEX, (0x00,0xFFFFFFFF)
|
|
help : >
|
|
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
|
|
length : 0x04
|
|
value : {0, 0, 0, 0}
|
|
- PchPmSlpAMinAssert :
|
|
name : PCH Pm Slp A Min Assert
|
|
type : EditNum, HEX, (0x01,0x4)
|
|
help : >
|
|
SLP_A Minimum Assertion Width Policy. Default is 2S
|
|
length : 0x01
|
|
value : 0x4
|
|
- EcAvailable :
|
|
name : Embedded Controller Availability
|
|
type : Constant, Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
Describes whether Embedded Controller is availabile or not
|
|
length : 0x01
|
|
value : 0x1
|
|
- CpuCrashLogEnable :
|
|
name : CPU CrashLog support
|
|
type : Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
Enable CrashLog feature in CPU.
|
|
length : 0x01
|
|
value : 0x0
|
|
- CrashLogReporting :
|
|
name : CrashLog BERT Reporting
|
|
type : Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
Enable reporting CrashLog data in ACPI BERT. Requires FSP support for CrashLog Data Collection.
|
|
length : 0x01
|
|
value : 0x0
|
|
condition : $SILICON_CFG_DATA.CpuCrashLogEnable != 0
|
|
- OpioRecenter :
|
|
name : Opio Recentering Ctrl
|
|
type : Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
Opio Recentering Disabling for Pcie Latency Improvement
|
|
length : 0x01
|
|
value : 0x1
|
|
- L2QosEnumerationEn :
|
|
name : L2 QOS Enumeration
|
|
type : Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
Enable L2 Qos Enumerate
|
|
length : 0x01
|
|
value : 0x0
|
|
- IehMode :
|
|
name : IEH Mode
|
|
type : Combo
|
|
option : 0:Bypass, 1:Enable
|
|
help : >
|
|
Integrated Error Handler Mode
|
|
length : 0x01
|
|
value : 0x0
|
|
- D3HotEnable :
|
|
name : Enable D3 Hot in TCSS
|
|
type : Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
This policy will enable/disable D3 hot support in IOM
|
|
length : 0x01
|
|
value : 0x1
|
|
- D3ColdEnable :
|
|
name : Enable D3 Cold in TCSS
|
|
type : Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
This policy will enable/disable D3 cold support in IOM
|
|
length : 0x01
|
|
value : 0x1
|
|
- TcCstateLimit :
|
|
name : TC State in TCSS
|
|
type : Combo
|
|
option : 0:Disable, 1:1, 2:2, 4:4, 5:5, 6:6, 7:7, 10:10
|
|
help : >
|
|
TC C-State Limit in IOM
|
|
length : 0x01
|
|
value : 10
|
|
- VccSt :
|
|
name : VCCST request for IOM
|
|
type : Combo
|
|
option : $EN_DIS
|
|
help : >
|
|
This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
|
|
length : 0x01
|
|
value : 0x01 |