39 lines
1.5 KiB
Python
39 lines
1.5 KiB
Python
## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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tool_dir = os.path.realpath(os.path.join(os.path.dirname (os.path.realpath(__file__)), '..', 'AlderlakeBoardPkg'))
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sys.path.append (tool_dir)
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import BoardConfig as AlderlakeBoardConfig
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class Board(AlderlakeBoardConfig.Board):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_ADLP'
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self.BOARD_NAME = 'adlp'
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 3
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self._EXTRA_INC_PATH = ['Silicon/AlderlakePkg/Adlp/Include']
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self._FSP_PATH_NAME = 'Silicon/AlderlakePkg/Adlp/FspBin'
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self.MICROCODE_INF_FILE = 'Silicon/AlderlakePkg/Microcode/Microcode.inf'
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self.ACPI_TABLE_INF_FILE = 'Platform/AlderlakeBoardPkg/AcpiTables/AcpiTablesP.inf'
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self.ENABLE_TCC = 0
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self._generated_cfg_file_prefix = ''
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self._CFGDATA_EXT_FILE = ['CfgDataInt_Adlp_Crb_Ddr5.dlt', 'CfgDataInt_Adlp_Crb_Lpddr5.dlt', 'CfgDataInt_Adlp_Crb_Lpddr4.dlt', 'CfgDataExt_Upx12.dlt']
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self._MULTI_VBT_FILE = {2:'VbtAdlP.dat', 3:'VbtAdlPUpx.dat'}
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self._LP_SUPPORT = True
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# 0 - PCH UART0, 1 - PCH UART1, 2 - PCH UART2, 0xFF - EC UART 0x3F8
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self.DEBUG_PORT_NUMBER = 0x0
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