224 lines
8.6 KiB
C
224 lines
8.6 KiB
C
/** @file
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This file contains define definitions specific to processor
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Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _POWER_MGMT_DEFINITIONS_H_
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#define _POWER_MGMT_DEFINITIONS_H_
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//
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// Voltage offset definitions
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//
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#define OC_LIB_OFFSET_ADAPTIVE 0
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#define OC_LIB_OFFSET_OVERRIDE 1
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//
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// Platform Power Management Flags Bit Definitions:
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// These defines are also used in CPU0CST.ASL to check platform configuration
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// and build C-state table accordingly.
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//
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#ifdef __GNUC__
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//
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// @todo Add workaround for GCC build, In GCC build the BIT can not be changed to value by GCC (ex: BIT0 can not be changed to 0x1)
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//
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#define PPM_EIST 0x1 ///< BIT 0 : Enhanced Intel Speed Step Technology.
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#define PPM_C1 0x2 ///< BIT 1 : C1 enabled, supported.
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#define PPM_C1E 0x4 ///< BIT 2 : C1E enabled.
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#define PPM_C6 0x10 ///< BIT 4 : C6 enabled, supported.
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#define PPM_C7 0x20 ///< BIT 5 : C7 enabled, supported.
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#define PPM_C7S 0x40 ///< BIT 6 : C7S enabled, supported
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#define PPM_TM 0x80 ///< BIT 7 : Adaptive Thermal Monitor.
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#define PPM_TURBO 0x100 ///< BIT 8 : Long duration turbo mode
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#define PPM_CMP 0x200 ///< BIT 9 : CMP.
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#define PPM_TSTATES 0x400 ///< BIT 10: CPU throttling states
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#define PPM_MWAIT_EXT 0x800 ///< BIT 11: MONITIOR/MWAIT Extensions supported.
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#define PPM_EEPST 0x1000 ///< BIT 12: Energy efficient P-State Feature enabled
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#define PPM_TSTATE_FINE_GRAINED 0x2000 ///< BIT 13: Fine grained CPU Throttling states
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#define PPM_CD 0x4000 ///< BIT 14: Deep Cstate - C8/C9/C10
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#define PPM_TIMED_MWAIT 0x8000 ///< BIT 15: Timed Mwait support
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#define C6_LONG_LATENCY_ENABLE 0x10000 ///< BIT 16: 1=C6 Long and Short,0=C6 Short only
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#define C7_LONG_LATENCY_ENABLE 0x20000 ///< BIT 17: 1=C7 Long and Short,0=C7 Short only
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#define C7s_LONG_LATENCY_ENABLE 0x40000 ///< BIT 18: 1=C7s Long and Short,0=C7s Short only
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#define PPM_C8 0x80000 ///< Bit 19: 1= C8 enabled/supported
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#define PPM_C9 0x100000 ///< Bit 20: 1= C9 enabled/supported
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#define PPM_C10 0x200000 ///< Bit 21: 1= C10 enabled/supported
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#define PPM_HWP 0x400000 ///< Bit 22: 1= HWP enabled/supported
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#define PPM_OC_UNLOCKED 0x1000000 ///< Bit 24: 1= Overclocking fully uncloked
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#define PPM_TURBO_BOOST_MAX 0x2000000 ///< Bit 25: 1= Intel Turbo Boost Max Technology 3.0.
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#else
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#define PPM_EIST BIT0 ///< Enhanced Intel Speed Step Technology.
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#define PPM_C1 BIT1 ///< C1 enabled, supported.
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#define PPM_C1E BIT2 ///< C1E enabled.
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#define PPM_C6 BIT4 ///< C6 enabled, supported.
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#define PPM_C7 BIT5 ///< C7 enabled, supported.
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#define PPM_C7S BIT6 ///< C7S enabled, supported
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#define PPM_TM BIT7 ///< Adaptive Thermal Monitor.
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#define PPM_TURBO BIT8 ///< Long duration turbo mode
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#define PPM_CMP BIT9 ///< CMP.
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#define PPM_TSTATES BIT10 ///< CPU throttling states
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#define PPM_MWAIT_EXT BIT11 ///< MONITIOR/MWAIT Extensions supported.
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#define PPM_EEPST BIT12 ///< Energy efficient P-State Feature enabled
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#define PPM_TSTATE_FINE_GRAINED BIT13 ///< Fine grained CPU Throttling states
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#define PPM_CD BIT14 ///< Deep Cstate - C8/C9/C10
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#define PPM_TIMED_MWAIT BIT15 ///< Timed Mwait support
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#define C6_LONG_LATENCY_ENABLE BIT16 ///< 1=C6 Long and Short,0=C6 Short only
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#define C7_LONG_LATENCY_ENABLE BIT17 ///< 1=C7 Long and Short,0=C7 Short only
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#define C7s_LONG_LATENCY_ENABLE BIT18 ///< 1=C7s Long and Short,0=C7s Short only
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#define PPM_C8 BIT19 ///< 1= C8 enabled/supported
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#define PPM_C9 BIT20 ///< 1= C9 enabled/supported
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#define PPM_C10 BIT21 ///< 1= C10 enabled/supported
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#define PPM_HWP BIT22 ///< 1= HWP enabled/supported
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#define PPM_OC_UNLOCKED BIT24 ///< 1= Overclocking fully unlocked
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#define PPM_TURBO_BOOST_MAX BIT25 ///< 1= Intel Turbo Boost Max Technology 3.0
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#endif
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#define PPM_C_STATES 0x7A ///< PPM_C1 + PPM_C3 + PPM_C6 + PPM_C7 + PPM_C7S
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//
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// The following definitions are based on assumed location for the ACPI
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// Base Address. Modify as necessary base on platform-specific requirements.
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//
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#define PCH_ACPI_PBLK 0x1810
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#define PCH_ACPI_LV3 0x1815
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#define PCH_ACPI_LV4 0x1816
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#define PCH_ACPI_LV6 0x1818
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#define PCH_ACPI_LV5 0x1817
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#define PCH_ACPI_LV7 0x1819
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//
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// C-State Latency (us) and Power (mW) for C1
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//
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#define C1_LATENCY 1
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#define C1_POWER 0x3E8
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#define C6_POWER 0x15E
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#define C7_POWER 0xC8
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#define C8_POWER 0xC8
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#define C9_POWER 0xC8
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#define C10_POWER 0xC8
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#ifndef AUTO
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#define AUTO 0
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#endif
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#define END_OF_TABLE 0xFF
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///
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/// For Desktop, default PL1 time window value is 8 second
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///
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#define DT_POWER_LIMIT1_TIME_DEFAULT 8
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#define VR_IMON_SLOPE_OFFSET 16
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#define SVID_REGISTER_VR_ID_VIRTUAL_0 4
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#define SVID_REGISTER_VR_ID_VIRTUAL_1 5
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#define SVID_EXCLUSIVE_DISABLE 0
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#define ELIXIR_PRODUCT_REV_MAILBOX_ADDRESS 2
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//24MHz XTAL Clock Frequency
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#define N_RFI_FREQ_LO_PF2_OFFSET 2
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#define N_RFI_FREQ_HI_PF2_OFFSET 16
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#define B_RFI_FREQ_PF2_MASK (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT3 | BIT2)
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#define N_RFI_FREQ_LO_PF2_OFFSET 2
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#define N_RFI_FREQ_HI_PF2_OFFSET 16
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#define B_RFI_FREQ_PF2_MASK (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT3 | BIT2)
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///
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/// Used to identify the CPU used for programming with the VR override table
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///
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typedef enum {
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EnumUnknownCpuId = 0,
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EnumMinCpuId = 1,
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///
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/// TGL-Y
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///
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EnumTglY9WattES1NoExsCpuId = 0x1,
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EnumTglY9Watt42fNoExsCpuId = 0x2,
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EnumTglY9WattES1ExsCpuId = 0x3,
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EnumTglY9Watt42fExsCpuId = 0x4,
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EnumTglYMaxCpuId = EnumTglY9Watt42fExsCpuId,
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///
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/// TGL-U
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///
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EnumTglU15WattES1NoExsCpuId = 0x5,
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EnumTglU15Watt42fNoExsCpuId = 0x6,
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EnumTglU28WattES1NoExsCpuId = 0x7,
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EnumTglU28Watt42fNoExsCpuId = 0x8,
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EnumTglU28Watt42fExsCpuId = 0x9,
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EnumTglU28WattES1ExsCpuId = 0xA,
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EnumTglU15WattES1ExsCpuId = 0xB,
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EnumTglU15Watt42fExsCpuId = 0xC,
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EnumTglUMaxCpuId = EnumTglU15Watt42fExsCpuId,
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///
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/// TGL-H
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///
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EnumTglH45Watt81ExsCpuId = 0xD,
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EnumTglH45Watt81NoExsCpuId = 0xE,
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EnumTglH65Watt81ExsCpuId = 0xF,
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EnumTglH65Watt81NoExsCpuId = 0x10,
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EnumTglH95Watt81ExsCpuId = 0x11,
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EnumTglH95Watt81NoExsCpuId = 0x12,
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EnumTglHMaxCpuId = EnumTglH95Watt81NoExsCpuId,
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///
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/// WHL
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///
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EnumWhlU15Watt42fCpuId = 0x20,
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EnumWhlU15Watt22fCpuId = 0x1E,
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EnumWhlU15Watt2f1fCpuId = 0x21,
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EnumWhlUMaxCpuId = EnumWhlU15Watt2f1fCpuId,
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EnumMaxCpuId = EnumWhlUMaxCpuId,
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} CPU_OVERRIDE_IDENTIFIER;
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///
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/// VR Override table structure
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///
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typedef struct {
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CPU_OVERRIDE_IDENTIFIER CpuIdentifier;
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UINT16 IaIccMax;
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UINT16 GtIccMax;
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UINT16 SaIccMax;
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UINT16 VccInIccMax;
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UINT16 IaTdclimit;
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UINT16 GtTdclimit;
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UINT16 SaTdclimit;
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UINT16 VccInTdclimit;
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UINT16 IaAcLoadLine;
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UINT16 IaDcLoadLine;
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UINT16 GtAcLoadLine;
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UINT16 GtDcLoadLine;
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UINT16 SaAcLoadLine;
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UINT16 SaDcLoadLine;
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UINT16 VccInAcLoadLine;
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UINT16 VccInDcLoadLine;
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UINT16 VrVoltageLimit;
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} CPU_VR_OVERRIDE_TABLE;
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#pragma pack (1)
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typedef struct {
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UINT8 NameOp; // 12h ;First opcode is a NameOp.
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UINT8 PackageLead; // 20h ;First opcode is a NameOp.
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UINT8 NumEntries; // 06h ;First opcode is a NameOp.
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UINT8 DwordPrefix1; // 0Ch
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UINT32 CoreFrequency; // 00h
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UINT8 DwordPrefix2; // 0Ch
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UINT32 Power; // 00h
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UINT8 DwordPrefix3; // 0Ch
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UINT32 TransLatency; // 00h
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UINT8 DwordPrefix4; // 0Ch
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UINT32 BmLatency; // 00h
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UINT8 DwordPrefix5; // 0Ch
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UINT32 Control; // 00h
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UINT8 DwordPrefix6; // 0Ch
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UINT32 Status; // 00h
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} PSS_PACKAGE_LAYOUT;
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#pragma pack()
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#endif
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