0c82e73533
This patch fixes no activity on UART0 pins when enabling it for serial communication. In TGL, there are two UART0 instances (GPP_C8~C11 and GPP_F0~F4) while one (GPP_F0~F4) is shared with CNVI. This patch enables GPP_C8~C11 as the UART0 instance to reduce the conflict with CNVI. This patch also fixes the GPIO pins definition for TGL-H and moves serial io initialization code to SerialIo.c to simplfy Stage2BoardInitLib.c. Test: TGL-UP3 RVP and TGL-H RVP Signed-off-by: Stanley Chang <stanley.chang@intel.com> |
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GpioPinsVer2H.h | ||
GpioPinsVer2Lp.h |