218 lines
11 KiB
C
218 lines
11 KiB
C
/** @file
|
|
PCIe Config Block
|
|
|
|
Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.<BR>
|
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
**/
|
|
#ifndef _PCIE_CONFIG_H_
|
|
#define _PCIE_CONFIG_H_
|
|
#include <CpuPcieInfo.h>
|
|
|
|
#define PCIE_CONFIG_REVISION 3
|
|
/*
|
|
<b>Revision 2< / b>:
|
|
FomsCp - Deprecated
|
|
<b>Revision 3< / b>:
|
|
Added PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
|
|
Added PCIE_EQ_PARAM HwEqGen4CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
|
|
Added PCIE_EQ_PARAM HwEqGen5CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
|
|
*/
|
|
|
|
extern EFI_GUID gPcieConfigGuid;
|
|
|
|
#pragma pack (push,1)
|
|
|
|
enum PCIE_COMPLETION_TIMEOUT {
|
|
PcieCompletionTO_Default,
|
|
PcieCompletionTO_50_100us,
|
|
PcieCompletionTO_1_10ms,
|
|
PcieCompletionTO_16_55ms,
|
|
PcieCompletionTO_65_210ms,
|
|
PcieCompletionTO_260_900ms,
|
|
PcieCompletionTO_1_3P5s,
|
|
PcieCompletionTO_4_13s,
|
|
PcieCompletionTO_17_64s,
|
|
PcieCompletionTO_Disabled
|
|
};
|
|
|
|
enum PCIE_SPEED {
|
|
PcieAuto,
|
|
PcieGen1,
|
|
PcieGen2,
|
|
PcieGen3,
|
|
PcieGen4
|
|
};
|
|
|
|
/**
|
|
Represent lane specific PCIe Gen3 equalization parameters.
|
|
**/
|
|
typedef struct {
|
|
UINT8 Cm; ///< Coefficient C-1
|
|
UINT8 Cp; ///< Coefficient C+1
|
|
UINT8 Rsvd0[2]; ///< Reserved bytes
|
|
} PCIE_EQ_PARAM;
|
|
|
|
typedef struct {
|
|
UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
|
|
UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
|
|
UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
|
|
UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
|
|
UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
|
|
UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
|
|
UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
|
|
UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
|
|
UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
|
|
UINT8 ForceLtrOverride;
|
|
UINT16 RsvdByte1;
|
|
} PCIE_LTR_CONFIG;
|
|
|
|
|
|
/**
|
|
Specifies the form factor that the slot
|
|
implements. For custom form factors that
|
|
do not require any special handling please
|
|
set PcieFormFactorOther.
|
|
**/
|
|
typedef enum {
|
|
PcieFormFactorOther = 0,
|
|
PcieFormFactorCem,
|
|
PcieFormFactorMiniPci,
|
|
PcieFormFactorM2,
|
|
PcieFormFactorOcuLink,
|
|
PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
|
|
PcieFormFactorExpressCard,
|
|
PcieFormFactorU2 // Also known as SF-8639
|
|
} PCIE_FORM_FACTOR;
|
|
|
|
//Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
|
|
typedef struct {
|
|
UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
|
|
UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
|
|
//
|
|
// Error handlings
|
|
//
|
|
UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
|
|
UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
|
|
/**
|
|
Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
|
|
Changes Max Payload Size Supported field in Device Capabilities of the root port.
|
|
**/
|
|
UINT32 MaxPayload : 2;
|
|
UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
|
|
UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
|
|
/**
|
|
Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
|
|
Built-in is incompatible with hotplug-capable ports.
|
|
**/
|
|
UINT32 SlotImplemented : 1;
|
|
UINT32 PtmEnabled : 1; ///< Enables PTM capability
|
|
UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
|
|
UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
|
|
/**
|
|
Probe CLKREQ# signal before enabling CLKREQ# based power management.
|
|
Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
|
|
to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
|
|
In particular this helps to avoid issues with open-ended PCIe slots.
|
|
This is only applicable to non hot-plug ports.
|
|
<b>0: Disable</b>; 1: Enable.
|
|
**/
|
|
UINT32 ClkReqDetect : 1;
|
|
/**
|
|
Set if the slot supports manually operated retention latch.
|
|
**/
|
|
UINT32 MrlSensorPresent : 1;
|
|
UINT32 RelaxedOrder : 1;
|
|
UINT32 NoSnoop : 1;
|
|
UINT32 RsvdBits0 : 28; ///< Reserved bits.
|
|
/**
|
|
PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
|
|
0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
|
|
**/
|
|
UINT8 Gen3EqPh3Method;
|
|
UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
|
|
UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
|
|
//
|
|
// Power Management
|
|
//
|
|
UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
|
|
UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
|
|
UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
|
|
UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
|
|
UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
|
|
/**
|
|
<b>(Test)</b>
|
|
Forces LTR override to be permanent
|
|
The default way LTR override works is:
|
|
rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
|
|
This settings allows force override of LTR mechanism. If it's enabled, then:
|
|
rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
|
|
**/
|
|
PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
|
|
/**
|
|
The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
|
|
before assuming there is no device and potentially disabling the port.
|
|
It's assumed that the link will exit detect state before root port initialization (sufficient time
|
|
elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
|
|
if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
|
|
In case of non-common clock enabled the default timout is 15ms.
|
|
<b>Default: 0</b>
|
|
**/
|
|
UINT16 DetectTimeoutMs;
|
|
UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
|
|
UINT8 Reserved;
|
|
} PCIE_ROOT_PORT_COMMON_CONFIG;
|
|
|
|
/**
|
|
PCIe Common Config
|
|
@note This structure will be expanded to hold all common PCIe policies between SA and PCH
|
|
**/
|
|
typedef struct {
|
|
///
|
|
/// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
|
|
///
|
|
UINT32 EnablePeerMemoryWrite : 1;
|
|
/**
|
|
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
|
|
A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
|
|
BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
|
|
- <b>Enabled: One of enabled root ports get assigned to Function0.</b>
|
|
This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
|
|
- Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
|
|
That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
|
|
NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
|
|
In other words, it only affects ports that would become hidden because they have no device connected.
|
|
NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
|
|
be used when each one of root ports 1, 9, 17:
|
|
- is configured as PCIe and has correctly configured ClkReq signal, or
|
|
- does not own any mPhy lanes (they are configured as SATA or USB)
|
|
**/
|
|
UINT32 RpFunctionSwap : 1;
|
|
/**
|
|
Compliance Test Mode shall be enabled when using Compliance Load Board.
|
|
<b>0: Disable</b>, 1: Enable
|
|
**/
|
|
UINT32 ComplianceTestMode : 1;
|
|
UINT32 RsvdBits0 : 29; ///< Reserved bits
|
|
///
|
|
/// List of coefficients used during equalization (applicable to both software and hardware EQ)
|
|
/// Deprecated Policy
|
|
///
|
|
PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
|
|
} PCIE_COMMON_CONFIG;
|
|
|
|
typedef struct {
|
|
PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
|
|
PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
|
|
} PCIE_COMMON_CONFIG2;
|
|
|
|
#pragma pack (pop)
|
|
#endif // _PCIE_CONFIG_H_
|