403 lines
25 KiB
Python
403 lines
25 KiB
Python
## @ StitchIfwiConfig.py
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# This is an IFWI stitch config script for RPL Slim Bootloader
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#
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# Copyright (c) 2023, Intel Corporation. All rights reserved. <BR>
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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import sys
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import os
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extra_usage_txt = \
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"""This is an IFWI stitch config script for Slim Bootloader For the FIT tool and
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stitching ingredients listed in step 2 below, please contact your Intel representative.
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1. Create a stitching workspace directory. The paths mentioned below are all
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relative to it.
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2. Extract required tools and ingredients to stitching workspace.
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- FIT tool
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Copy 'fit.exe' or 'fit' and 'vsccommn.bin' to 'Fit' folder
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- BPMGEN2 Tool
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Copy the contents of the tool to Bpmgen2 folder
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Rename the bpmgen2 parameter to bpmgen2.params if its name is not this name.
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- Components
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Copy 'cse_image.bin' to 'Input/cse_image.bin'
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Copy PMC firmware image to 'Input/pmc.bin'.
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Copy EC firmware image to 'Input/ec.bin'.
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copy ECregionpointer.bin to 'Input/ecregionpointer.bin'
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Copy GBE binary image to 'Input/gbe.bin'.
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Copy ACM firmware image to 'Input/acm.bin'.
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Copy DiagnosticACM firmware image to 'Input/DiagnosticAcm.bin'.
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3. Openssl
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Openssl is required for stitch. the stitch tool will search evn OPENSSL_PATH,
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to find Openssl. If evn OPENSSL_PATH is not found, will find openssl from
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"C:\\Openssl\\Openssl"
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4. Stitch the final image
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EX:
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Assuming stitching workspace is at D:\Stitch and building ifwi for RPL platform
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To stitch IFWI with SPI QUAD mode and Boot Guard profile VM:
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StitchIfwi.py -b vm -p rplp -w D:\Stitch -s Stitch_Components.zip -c StitchIfwiConfig.py
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"""
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def get_bpmgen2_params_change_list ():
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params_change_list = []
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params_change_list.append ([
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# variable | value |
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# ===================================
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('PlatformRules', 'ADL Client'),
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('BpmStrutVersion', '0x20'),
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('BpmRevision', '0x01'),
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('BpmRevocation', '1'),
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('AcmRevocation', '2'),
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('NEMPages', '3'),
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('AcpiBase', '0x1800'),
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('IbbFlags', '0x12'),
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('IbbHashAlgID', '0x0C:SHA384'),
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('TxtInclude', 'FALSE'),
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('PcdInclude', 'TRUE'),
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('BpmSigScheme', '0x16:RSAPSS'),
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('BpmSigPubKey', r'BpmGen2/keys/bpm_pubkey_3072.pem'),
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('BpmSigPrivKey', r'BpmGen2/keys/bpm_privkey_3072.pem'),
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('BpmKeySizeBits', '3072'),
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('BpmSigHashAlgID', '0x0C:SHA384'),
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])
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return params_change_list
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def get_platform_sku():
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platform_sku ={
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'rplp' : 'Intel(R) AlderLake P Chipset - Consumer - SPI',
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}
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return platform_sku
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def get_component_replace_list(plt_params_list):
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replace_list = [
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# Path file name compress Key SVN
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('IFWI/BIOS/TS0/ACM0', 'Input/acm0.bin', 'dummy', '', ''),
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('IFWI/BIOS/TS1/ACM0', 'Input/acm0.bin', 'dummy', '', ''),
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]
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if 'fusa' in plt_params_list:
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print("Replace the DACM")
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replace_list.extend ([
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('IFWI/BIOS/TS0/DACM', 'Input/DiagnosticAcm.bin', 'dummy', '', ''),
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('IFWI/BIOS/TS1/DACM', 'Input/DiagnosticAcm.bin', 'dummy', '', ''),
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])
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if 'tsn' in plt_params_list:
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if os.path.exists('IPFW/TsnSubRegion.bin'):
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print ("TsnSubRegion.bin found")
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replace_list.append (
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('IFWI/BIOS/NRD/IPFW/TMAC', 'IPFW/TsnSubRegion.bin', 'lz4', 'KEY_ID_CONTAINER_COMP_RSA3072', 0), # TSN MAC Address
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)
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if 'posc' in plt_params_list:
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if os.path.exists('IPFW/PreOsChecker.bin'):
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print ("PreOsChecker.bin found")
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replace_list.append (
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('IFWI/BIOS/NRD/IPFW/POSC', 'IPFW/PreOsChecker.bin', 'lz4', 'KEY_ID_CONTAINER_COMP_RSA3072', 0), # Pre-OS Checker binar
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)
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return replace_list
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def check_parameter(para_list):
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print (para_list)
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para_supported = {
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'lp4' : {},
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'lp5' : {},
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'ddr5' : {},
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'crb' : {},
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'sata' : {},
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'spi' : {'25MHz', '33MHz', '50MHz', '100MHz'},
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'tsn' : {'PCIe7','PCIe8'},
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'dual' : {},
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'64MB' : {},
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'debug' : {},
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'posc' : {},
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'fusa' : {}
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}
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para_help = \
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"""
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'lp4' -- Stitch for DDRLP4 board
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'lp5' -- Stitch for LPDDR5 board
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'ddr5' -- Stitch for DDR5 board
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'crb' -- Stitch for DDR5 COM-HPC CRB board
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'sata' -- Enable sata port0 and port1 support
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'spi' -- Set SPI frequency to be '25MHz', '33MHz', '50MHz' or '100MHz'. By default use 25Mhz.
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'tsn' -- Enable TSN softstraps for different TSN ports (either PCIe7 or PCIe8)
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'dual' -- Build For 2 flash components to allow space for FuSa BIST pattern data
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'64MB' -- Build for 64MB component to allow space for FuSa BIST pattern data
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'debug' -- Enable DAM and DCI
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'posc' -- Stitch POSC binary into BIOS region.
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'fusa' -- Stitch Fusa DiagnosticAcm binary into BIOS region
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"""
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for para in para_list:
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if para == '':
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print ("No platform specific parameter provided")
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return True
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if para not in para_supported:
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print ("NOT support platform parameter: %s" % para)
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print ("platform parameter list:\n")
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print (para_help)
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return False
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if para_list[para] != None:
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if para_list[para] not in para_supported[para]:
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print ("NOT support platform parameter: %s" % para_list[para])
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print ("platform parameter list:", para_supported[para])
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return False
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if para == 'tsn':
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if para_list[para] == None:
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print ("TSN option expects a PCIe Port value")
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print (para_help)
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return False
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return True
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def get_oemkeymanifest_change_list():
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xml_change_list = []
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xml_change_list.append ([
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# Path | value |
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# =========================================================================================
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('./KeyManifestEntries/KeyManifestEntry/Usage', 'OemDebugManifest'),
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('./KeyManifestEntries/KeyManifestEntry/HashBinary', 'Temp/kmsigpubkey.hash'),
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])
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return xml_change_list
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def get_xml_change_list (platform, plt_params_list):
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xml_change_list = []
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xml_change_list.append ([
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# Path | value |
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# =========================================================================================
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('./BuildSettings/HarnessGlobalData/SelectedRvp', 'RPL-P DDR5 (RPL-P + ADP-P)'),
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('./FlashLayout/BiosRegion/InputFile', '$SourceDir\BiosRegion.bin'),
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('./FlashLayout/Ifwi_IntelMePmcRegion/MeRegionFile', '$SourceDir\MeRegionFile.bin'),
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('./FlashLayout/Ifwi_IntelMePmcRegion/PmcBinary', '$SourceDir\PmcBinary.bin'),
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('./FlashLayout/Ifwi_IntelMePmcRegion/ChipInitBinary', '$SourceDir\ChipInitBinary.bin'),
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('./FlashLayout/EcRegion/EcRegionPointer', '$SourceDir\EcRegionPointer.bin'),
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('./FlashLayout/EcRegion/InputFile', '$SourceDir\EcRegion.bin'),
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('./FlashLayout/EcRegion/Enabled', 'Enabled'),
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('./FlashLayout/GbeRegion/InputFile', '$SourceDir\GbeRegion.bin'),
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('./FlashLayout/GbeRegion/Enabled', 'Enabled'),
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('./FlashLayout/SubPartitions/IunitSubPartition/InputFile', '$SourceDir\IunitSubPartition.bin'),
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('./FlashLayout/SubPartitions/PchcSubPartitionData/InputFile', '$SourceDir\PchcSubPartitionData.bin'),
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('./FlashSettings/FlashConfiguration/QuadOutReadEnable', 'Yes'),
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('./FlashSettings/FlashConfiguration/QuadIoReadEnable', 'Yes'),
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('./FlashSettings/VsccTable/VsccEntries/VsccEntry/VsccEntryName', 'VsccEntry0'),
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('./FlashSettings/BiosConfiguration/BiosRedAssistance', 'Disabled'),
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('./PlatformProtection/PlatformIntegrity/OemExtInputFile', '$SourceDir\OemExtInputFile.bin'),
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('./PlatformProtection/PlatformIntegrity/OemPublicKeyHash', 'F8 F0 E3 69 15 81 76 99 0A 54 9E D4 C3 6D 1A 86 39 D8 87 3D EF F7 ED 2D E3 4C B4 1B CC B3 04 76 CE 0A A0 63 BC 5B 7A AC FF D9 50 9E 96 40 C6 99'),
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('./PlatformProtection/BootGuardConfiguration/BtGuardKeyManifestId', '0x1'),
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('./PlatformProtection/BiosGuardConfiguration/BiosGrdProtOvrdEn', 'Yes'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC0', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC1', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC2', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC3', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC4', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC5', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC6', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC7', 'Enabled'),
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('./NetworkingConnectivity/WiredLanConfiguration/PhyConnected', 'PHY on SMLink0'),
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('./IntegratedSensorHub/IshImage/InputFile', '$SourceDir\IshImage.bin'),
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('./IntegratedSensorHub/IshData/PdtBinary', '$SourceDir\PdtBinary.bin'),
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('./Debug/DelayedAuthenticationModeConfiguration/DelayedAuthMode', 'No'),
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('./FlexIO/Type-CSubsystemConfiguration/IomBinaryFile', '$SourceDir\IomBinaryFile.bin'),
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('./FlexIO/Type-CSubsystemConfiguration/PhyBinaryFile', '$SourceDir\PhyBinaryFile.bin'),
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('./FlexIO/Type-CSubsystemConfiguration/TbtBinaryFile', '$SourceDir\TbtBinaryFile.bin'),
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('./IntelUniquePlatformId/EntitlementsConfiguration/IcpsSwSkuing', 'Yes'),
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('./FlexIO/Usb3PortConfiguration/USB3Port4SpdCap', 'USB 3.1 Gen1'),
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('./FlexIO/Type-CSubsystemConfiguration/XdciSplitDieConfig', 'xDCI Split Die Disabled'),
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('./FlashSettings/FlashConfiguration/FastReadClockFreq', '25MHz'),
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('./FlashSettings/FlashConfiguration/ReadIdAndReadStatClkFreq', '25MHz'),
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('./FlashSettings/FlashConfiguration/WriteEraseClockFreq', '25MHz'),
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])
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if 'dual' in plt_params_list:
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xml_change_list.append ([
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('./BuildSettings/BuildResults/NumberOfFlashComponents', '2'),
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('./BuildSettings/BuildResults/FlashComponentsSizes', '32,32'),
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])
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if '64MB' in plt_params_list:
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raise Exception('ERROR: dual 64MB flash not supported!')
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if '64MB' in plt_params_list:
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xml_change_list.append ([
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('./BuildSettings/BuildResults/FlashComponentsSizes', '64'),
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])
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if 'lp4' in plt_params_list:
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xml_change_list.append ([
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('./BuildSettings/HarnessGlobalData/SelectedRvp', 'ADL-P LP4x (ADL-P + ADP-P)'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC8', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC9', 'Enabled'),
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('./NetworkingConnectivity/WirelessLanConfiguration/MeClinkEnable', 'No'),
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('./Camera/IPUSecurity/SecureTouchCameraMask', '0x0'),
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])
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if 'ddr5' in plt_params_list:
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xml_change_list.append ([
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1SmbusAddr', '0x50'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2SMBusAddr', '0x51'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort3SmbusAddr', '0x52'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort4SmbusAddr', '0x53'),
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('./Gpio/GpioVccioVoltageControl/GppE7voltSelect', '1.8Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH15voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppA21voltSelect', '1.8Volts'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC8', 'Enabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC9', 'Enabled'),
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('./PlatformProtection/TpmOverSpiBusConfiguration/SpiOverTpmBusEnable', 'No'),
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])
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if 'crb' in plt_params_list:
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xml_change_list.append ([
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('./BuildSettings/BuildResults/Sku', 'Premium'),
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('./BuildSettings/HarnessGlobalData/SelectedRvp', 'RPL-P DDR5 (RPL-P + ADP-P)'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1SmbusAddr', '0x50'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2SMBusAddr', '0x0'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort3SmbusAddr', '0x52'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort4SmbusAddr', '0x53'),
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('./Gpio/GpioVccioVoltageControl/GppE2voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppE10voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppE11voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppE12voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppE13voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppE15voltSelect', '1.8Volts'),
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('./Gpio/GpioVccioVoltageControl/GppE16voltSelect', '1.8Volts'),
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('./Gpio/GpioVccioVoltageControl/GppE17voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppA21voltSelect', '1.8Volts'),
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('./Gpio/GpioVccioVoltageControl/GppF6voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppF11voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppF12voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppF13voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppF16voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppF17voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppF18voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppD1voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppD2voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppD3voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH3voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH4voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH5voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH8voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH12voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppH15voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppB7voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppB8voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppB14voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppB15voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppB23voltSelect', '3.3Volts'),
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('./Gpio/GpioVccioVoltageControl/GppT2voltSelect', '1.8Volts'),
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('./Gpio/GpioVccioVoltageControl/GppT3voltSelect', '1.8Volts'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC1', 'Disabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC5', 'Disabled'),
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('./Icc/IccPolicies/Profiles/Profile/ClockOutputConfiguration/ClkoutSRC7', 'Disabled'),
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('./CpuStraps/CpuStraps/Vccp105CpuPg', 'VCCP 1.05 CPU PG Not present'),
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('./NetworkingConnectivity/WiredLanConfiguration/GbePCIePortSelect', 'Port8'),
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('./NetworkingConnectivity/WirelessLanConfiguration/CnviWlanCrdEn', 'Disabled'),
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('./NetworkingConnectivity/WirelessLanConfiguration/MEWlanPowerWell', 'Primary Well || SLP_SUS#'),
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('./FlashSettings/FlashConfiguration/SpiDualOutReadEnable', 'Yes'),
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('./FlashSettings/FlashConfiguration/SpiDualIoReadEnable', 'Yes'),
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('./Gpio/ThunderboltLsxBssb-LsConfiguration/TbltLsxBssbLs0Cfg', 'Legacy VCCIO'),
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('./Gpio/ThunderboltLsxBssb-LsConfiguration/TbltLsxBssbLs1Cfg', 'Legacy VCCIO'),
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('./Power/DeepSx/DeepSxSupportEnable', 'No'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1Mode', 'No'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1RetimerEnabled', 'No'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1SmbusAddr', '0x0'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2Mode', 'No'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2RetimerEnabled', 'No'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/USB2PortForTypeCPort2', 'USB2 Port 1'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort3SmbusAddr', '0x21'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/USB2PortForTypeCPort3', 'USB2 Port 1'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort4SmbusAddr', '0x25'),
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('./FlexIO/PowerDelivery_PdControllerConfiguration/USB2PortForTypeCPort4', 'USB2 Port 2'),
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('./FlexIO/Type-CSubsystemConfiguration/TypeCPort1Config', 'DP Fixed Connection'),
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('./FlexIO/Type-CSubsystemConfiguration/TypeCPort2Config', 'DP Fixed Connection'),
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('./FlexIO/PciePortConfiguration/PCIeController2Config', '1x2, 2x1'),
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('./FlexIO/PciePortConfiguration/PCIeController3Config', '4x1'),
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('./FlexIO/Usb3PortConfiguration/USB3Port1SpdCap', 'USB 3.1 Gen1'),
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('./FlexIO/Usb3PortConfiguration/USB3Port2SpdCap', 'USB 3.1 Gen1'),
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('./FlexIO/Usb3PortConfiguration/USB3Port3SpdCap', 'USB 3.1 Gen1'),
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('./FlexIO/Usb3PortConfiguration/USB3Prt4ConTypeSel', 'Type A / Type C'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt3ConTypeSel', 'Type A / Type C'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt4ConTypeSel', 'Type A / Type C'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt5ConTypeSel', 'Type A / Type C'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt7ConTypeSel', 'Express Card / M.2 S2'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt8ConTypeSel', 'Express Card / M.2 S2'),
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('./FlexIO/Usb2PortConfiguration/USB2Prt10ConTypeSel', 'Type A / Type C'),
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('./Camera/IPUSecurity/SecureTouchCameraMask', '0x0'),
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('./Debug/DirectConnectInterfaceConfiguration/Usb4DciOobEnable', 'Yes'),
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])
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if 'lp5' in plt_params_list:
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xml_change_list.append ([
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('./BuildSettings/HarnessGlobalData/SelectedRvp', 'RPL-P LP5 (RPL-P + ADP-P)'),
|
|
('./IntelMeKernel/IntelMeBootConfiguration/PrtcBackupPower', 'None'),
|
|
('./InternalPchBuses/EspiConfiguration/EspiEcSlvAtchdFlshMor', 'Multiple Outstanding Requests'),
|
|
('./FlexIO/Type-CSubsystemConfiguration/TypeCPort3Config', 'No Thunderbolt'),
|
|
('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort1RetimerConfig', 'Yes'),
|
|
('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort2RetimerConfig', 'Yes'),
|
|
('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort3RetimerEnabled', 'No'),
|
|
('./FlexIO/PowerDelivery_PdControllerConfiguration/TypeCPort4RetimerConfig', 'Yes'),
|
|
('./Gpio/GpioVccioVoltageControl/GppE7voltSelect', '1.8Volts'),
|
|
('./PlatformProtection/TpmOverSpiBusConfiguration/SpiOverTpmBusEnable', 'No'),
|
|
('./FlexIO/Type-CSubsystemConfiguration/TypeCPort2Config', 'DP Fixed Connection'),
|
|
('./FlexIO/UfsConfiguration/UfsCont1Config', 'X1'),
|
|
('./Gpio/ThunderboltLsxBssb-LsConfiguration/TbltLsxBssbLs1Cfg', 'Legacy VCCIO'),
|
|
])
|
|
|
|
if 'tsn' in plt_params_list:
|
|
tsn = plt_params_list.get('tsn')
|
|
print ("Applying changes to set tsn setting to %s" % tsn)
|
|
if tsn == 'PCIe7':
|
|
xml_change_list.append ([
|
|
('./NetworkingConnectivity/TimeSensitiveNetworkingConfiguration/TsnEnabled', 'TSN on PCIe 7 Enabled'),
|
|
])
|
|
elif tsn == 'PCIe8':
|
|
xml_change_list.append ([
|
|
('./NetworkingConnectivity/TimeSensitiveNetworkingConfiguration/TsnEnabled', 'TSN on PCIe 8 Enabled'),
|
|
])
|
|
|
|
if 'spi' in plt_params_list:
|
|
frequency = plt_params_list.get('spi')
|
|
print ("Applying changes to set SPI frequency to %s" % frequency)
|
|
xml_change_list.append ([
|
|
('./FlashSettings/FlashConfiguration/FastReadClockFreq', frequency),
|
|
('./FlashSettings/FlashConfiguration/ReadIdAndReadStatClkFreq', frequency),
|
|
('./FlashSettings/FlashConfiguration/WriteEraseClockFreq', frequency),
|
|
])
|
|
|
|
if 'sata' in plt_params_list:
|
|
print ("Applying changes to enable sata")
|
|
xml_change_list.append ([
|
|
('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort0', 'SATA')])
|
|
# COM-HPC board only has SATA0 connected and has different bifurcation settings
|
|
if 'crb' not in plt_params_list:
|
|
xml_change_list.append ([
|
|
('./FlexIO/PciePortConfiguration/PCIeController3Config', '1x2, 2x1'),
|
|
('./FlexIO/SataPcieComboPortConfiguration/SataPCIeComboPort1', 'SATA'),
|
|
])
|
|
|
|
if 'debug' in plt_params_list:
|
|
print ("Applying changes to enable DAM and DCI")
|
|
xml_change_list.append ([
|
|
('./Debug/DelayedAuthenticationModeConfiguration/DelayedAuthMode', 'Yes'),
|
|
('./PlatformProtection/BootGuardConfiguration/BtGuardCpuDebugEnable', 'Enabled'),
|
|
('./Debug/DirectConnectInterfaceConfiguration/DciDbcEnable', 'Yes'),
|
|
('./Debug/DirectConnectInterfaceConfiguration/Usb1DciOobEnable', 'Yes'),
|
|
('./Debug/DirectConnectInterfaceConfiguration/Usb2DciOobEnable', 'Yes'),
|
|
('./Debug/DirectConnectInterfaceConfiguration/Usb3DciOobEnable', 'Yes'),
|
|
('./Debug/DirectConnectInterfaceConfiguration/Usb4DciOobEnable', 'Yes'),
|
|
('./Debug/IntelMeFirmwareDebuggingOverrides/DbgOverridePreProdSi', '0x7'),
|
|
('./Debug/IntelMeFirmwareDebuggingOverrides/DbgOverrideProdSi', '0x7'),
|
|
('./Debug/DirectConnectInterfaceConfiguration/Usb3DciOobEnable', 'Yes'),
|
|
])
|
|
return xml_change_list
|