228 lines
5.1 KiB
Plaintext
228 lines
5.1 KiB
Plaintext
/** @file
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Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuPowerMgmt.h"
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DefinitionBlock (
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"CPU0CST.aml",
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"SSDT",
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2,
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"PmRef",
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"Cpu0Cst",
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0x3001
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)
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{
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External(\_SB.PR00, DeviceObj)
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External(PWRS)
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External(CFGD)
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External(PF00)
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External(FMBL)
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External(FEMD)
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External(PFLV)
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External(C6MW) // Mwait Hint value for C6
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External(C7MW) // Mwait Hint value for C7
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External(CDMW) // Mwait Hint value for C8/C9/C10
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External(C6LT) // Latency Value for C6
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External(C7LT) // Latency Value for C7
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External(CDLT) // Latency Value for C8/C9/C10
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External(CDLV) // IO Level value for C8/C9/C10
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External(CDPW) // Power value for C8/C9/C10
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Scope(\_SB.PR00)
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{
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//
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// Create Temp packages for each C-state and Initialize them to default IO_LVL
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//
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// C1 Temp Package (C1 - HLT)
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//
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Name ( C1TM, Package()
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{
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ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},
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1,
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C1_LATENCY,
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C1_POWER
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})
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//
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// C6 Temp Package
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//
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Name ( C6TM, Package()
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{
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ResourceTemplate () {Register(SystemIO, 8, 0, PCH_ACPI_LV3)},
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2,
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0,
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C6_POWER
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})
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//
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// C7 Temp Package
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//
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Name ( C7TM, Package()
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{
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ResourceTemplate () {Register(SystemIO, 8, 0, PCH_ACPI_LV4)},
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2,
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0,
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C7_POWER
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})
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//
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// CD Temp Package - Deep C-states - covers C8/C9/C10
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//
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Name ( CDTM, Package()
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{
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ResourceTemplate () {Register(SystemIO, 8, 0, PCH_ACPI_LV4)},
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3,
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0,
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0
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})
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//
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// ResourceTemplate for MWait Extentions Supported.
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//
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Name ( MWES, ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)})
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//
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// Valid/Invalid Flags for ACPI C2 and C3
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//
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Name (AC2V, 0)
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Name (AC3V, 0)
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//
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// Package for reporting 3 C-states
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//
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Name ( C3ST, Package()
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{
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3,
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Package() {},
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Package() {},
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Package() {}
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})
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//
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// Package for reporting 2 C-states
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//
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Name ( C2ST, Package()
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{
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2,
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Package() {},
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Package() {}
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})
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//
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// Package for reporting 1 C-state
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//
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Name ( C1ST, Package()
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{
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1,
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Package() {}
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})
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//
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// C-state initialization flag
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//
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Name(CSTF, 0)
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//
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// Returns the C-state table based on platform configuration.
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// This method is serialized since it uses various global packages and updates them in run time to return the current C-state table.
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//
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Method (_CST, 0, Serialized)
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{
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If(LNot(CSTF))
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{
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//
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// First call to _CST.
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// Update Latency Values for C6/C7/CD based on the Latency values passed through PPM NVS
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//
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Store (C6LT, Index(C6TM, 2))
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Store (C7LT, Index(C7TM, 2))
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Store (CDLT, Index(CDTM, 2))
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//
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// Update the IO_LVL and Power values in CD temp package
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//
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Store (CDPW, Index(CDTM, 3))
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Store (CDLV, Index (DerefOf (Index (CDTM, 0)),7))
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//
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// CFGD[11] = 1 - MWAIT extensions supported
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// PDCx[9] = 1 - OS supports MWAIT extensions
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// PDCx[8] = 1 - OS supports MWAIT for C1 (Inferred from PDCx[9] = 1.)
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//
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If(LAnd(And(CFGD, PPM_MWAIT_EXT), And(PF00,0x200)))
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{
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//
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// Processor MWAIT extensions supported and OS supports MWAIT extensions
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// 1. Replace the IO LVL ResourceTemplate of C1TM, C6TM, C7TM, CDTM with MWAIT EXT ResourceTemplate (FFixedHW)
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// 2. Update the Mwait Hint Values for C6/C7/CD based on the Latency values passed through PPM NVS
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//
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Store (MWES, Index (C1TM, 0))
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Store (MWES, Index (C6TM, 0))
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Store (MWES, Index (C7TM, 0))
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Store (MWES, Index (CDTM, 0))
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Store (C6MW, Index (DerefOf (Index (C6TM, 0)),7))
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Store (C7MW, Index (DerefOf (Index (C7TM, 0)),7))
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Store (CDMW, Index (DerefOf (Index (CDTM, 0)),7))
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}
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ElseIf (LAnd(And(CFGD, PPM_MWAIT_EXT), And(PF00,0x100)))
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{
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//
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// Update C1 temp package ResourceTemplate if OS supports Mwait for C1
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//
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Store (MWES, Index (C1TM, 0))
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}
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Store (Ones, CSTF)
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}
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//
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// Initialize the ACPI C2, C3 Valid/Invalid flags to Invalid (0)
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//
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Store(Zero, AC2V)
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Store(Zero, AC3V)
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//
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// Create C state Package with Acpi C1= C1,ACPI C2=MaxSupported(C6,C3,C7),ACPI C3=MaxSupported(C8,C9,C10).
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// It is safe to assume C1 always supported if we enable C-states.
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//
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Store (C1TM, Index (C3ST,1))
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If(And(CFGD,PPM_C7))
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{
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Store (C7TM, Index (C3ST,2))
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Store (Ones, AC2V)
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}ElseIf(And(CFGD,PPM_C6))
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{
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Store (C6TM, Index (C3ST,2))
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Store (Ones, AC2V)
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}
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If(And(CFGD,PPM_CD)) {
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Store (CDTM, Index (C3ST,3))
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Store (Ones, AC3V)
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}
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//
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// Filter and return the final C-state package
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//
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If(LAnd(AC2V, AC3V))
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{
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Return (C3ST)
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}
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ElseIf(AC2V)
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{
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Store (DerefOf (Index (C3ST,1)), Index (C2ST,1))
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Store (DerefOf (Index (C3ST,2)), Index (C2ST,2))
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Return (C2ST)
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}
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ElseIf(AC3V)
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{
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Store (DerefOf (Index (C3ST,1)), Index (C2ST,1))
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Store (DerefOf (Index (C3ST,3)), Index (C2ST,2))
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Store (2, Index (DerefOf (Index (C2ST, 2)),1))
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Return (C2ST)
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}
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Else
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{
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Store (DerefOf (Index (C3ST,1)), Index (C1ST,1))
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Return (C1ST)
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}
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}
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}
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}
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