335 lines
15 KiB
Python
Executable File
335 lines
15 KiB
Python
Executable File
## @file
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# This file is used to provide board specific image information.
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#
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# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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# Import Modules
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#
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import os
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import sys
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sys.dont_write_bytecode = True
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sys.path.append (os.path.join('..', '..'))
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from BuildLoader import FLASH_MAP, BaseBoard, STITCH_OPS
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from BuildLoader import IPP_CRYPTO_OPTIMIZATION_MASK, IPP_CRYPTO_ALG_MASK, HASH_USAGE
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#
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# Temporary Memory Layout for APL
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#
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# FF000000 +--------------------------+
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# | Stage1B |
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# | (Decompressed) |
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# FEF80000 +--------------------------+
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# | Stage1 Heap/Stack |
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# FEF70000 +--------------------------+
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# | Not Used |
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# +-------------+------------+
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# | Free |
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# | |------------|
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# +-------------+ MRC NVS |
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# | | |
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# FEF40000 +- Stage1B -+------------+
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# | Compressed | FSP Mem |
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# FEF16000 | +------------+
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# | | |
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# FEF10000 --------------+------------+
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# | N/A (Don't use) |
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# FEF08000 +--------------------------+
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# | Stage1A |
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# FEF00000 +--------------------------+
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#
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class Board(BaseBoard):
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def __init__(self, *args, **kwargs):
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super(Board, self).__init__(*args, **kwargs)
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self.VERINFO_IMAGE_ID = 'SB_APLI '
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self.VERINFO_PROJ_MAJOR_VER = 1
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self.VERINFO_PROJ_MINOR_VER = 0
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self.VERINFO_SVN = 1
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self.VERINFO_BUILD_DATE = '05/20/2018'
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self.BOARD_NAME = 'apl'
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self.BOARD_PKG_NAME = 'ApollolakeBoardPkg'
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self.SILICON_PKG_NAME = 'ApollolakePkg'
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self._PCI_ENUM_DOWNGRADE_PMEM64 = 1
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self.PCI_IO_BASE = 0x00001000
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self.PCI_MEM32_BASE = 0x80000000
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self.PCI_MEM64_BASE = 0x400000000
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self.FLASH_SIZE = 0x800000
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self.FLASH_BASE = self.FLASH_LAYOUT_START - self.FLASH_SIZE
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self.HAVE_VBT_BIN = 1
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self.HAVE_VERIFIED_BOOT = 1
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self.HAVE_MEASURED_BOOT = 0
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self.HAVE_SEED_LIST = 0
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self.HAVE_PSD_TABLE = 1
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self.ENABLE_SMBIOS = 1
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self.ENABLE_FSP_LOAD_IMAGE = 0
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self.ENABLE_VTD = 1
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self.ENABLE_FWU = 1
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self.ENABLE_SPLASH = 1
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self.ENABLE_FRAMEBUFFER_INIT = 1
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self.ENABLE_GRUB_CONFIG = 1
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self.ENABLE_DMA_PROTECTION = 0
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self.ENABLE_SMM_REBASE = 2
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# G9 for 384 | W7 Opt for SHA384| Ni Opt for SHA256| V8 Opt for SHA256
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self.ENABLE_CRYPTO_SHA_OPT = IPP_CRYPTO_OPTIMIZATION_MASK['SHA256_NI']
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# To enable source debug, set 1 to self.ENABLE_SOURCE_DEBUG
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# self.ENABLE_SOURCE_DEBUG = 1
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# Temporary skip Stage1A due to 32KB(IBBL) size limitation
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# until library size optimization has done.
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# If ENABLE_SOURCE_DEBUG is disabled, SKIP_STAGE1A_SOURCE_DEBUG will be ignored
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self.SKIP_STAGE1A_SOURCE_DEBUG = 1
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# BIT0:Serial BIT1:USB KB
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# Support serial port input console by default
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self.CONSOLE_IN_DEVICE_MASK = 0x00000001
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# BIT0:Serial BIT1:GFX
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self.CONSOLE_OUT_DEVICE_MASK = 0x00000001
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# Mem | NVMe | Usb | Spi | Ufs | eMMC | SD | Sata
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self.BOOT_MEDIA_SUPPORT_MASK = 0xBF
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# EXT | FAT
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self.FILE_SYSTEM_SUPPORT_MASK = 3
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# Verify required minimum FSP version
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self.MIN_FSP_REVISION = 0x01040301
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# Verify FSP image ID. Empty string means skipping verification
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self.FSP_IMAGE_ID = '$APLFSP$'
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self.STAGE1A_SIZE = 0x00008000
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self.STAGE1B_SIZE = 0x00038000
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if self.ENABLE_SOURCE_DEBUG:
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self.STAGE1B_SIZE += 0x2000
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self.STAGE2_SIZE = 0x00034000
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self.PAYLOAD_SIZE = 0x00022000
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if len(self._PAYLOAD_NAME.split(';')) > 1:
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# EPAYLOAD is specified
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self.EPAYLOAD_SIZE = 0x00130000
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self.UEFI_VARIABLE_SIZE = 0x00040000
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else:
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# EPAYLOAD does not exist, create a dummy one
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self.EPAYLOAD_SIZE = 0x1000
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self.UEFI_VARIABLE_SIZE = 0x1000
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if self.FSPDEBUG_MODE == 1:
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self.STAGE1B_SIZE += 0x00009000
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self.STAGE2_SIZE += 0x0000F000
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self.STAGE1A_XIP = 0
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self.STAGE1A_LOAD_BASE = 0xFEF00000
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self.STAGE1B_XIP = 0
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self.REMAP_STAGE1B = 1
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self.STAGE1B_LOAD_BASE = 0xFEF10000
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self.STAGE1B_FD_BASE = 0xFEF80000
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self.STAGE1B_FD_SIZE = 0x0006D000
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if self.ENABLE_SOURCE_DEBUG:
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self.STAGE1B_FD_SIZE += 0x00001000
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if self.RELEASE_MODE == 0:
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self.STAGE1B_FD_SIZE += 0x00002000
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self.PAYLOAD_SIZE += 0x00007000
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# For Stage2, it is always compressed.
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# if STAGE2_LOAD_HIGH is 1, STAGE2_FD_BASE will be ignored
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self.STAGE2_FD_BASE = 0x01000000
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self.STAGE2_FD_SIZE = 0x00080000
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self.STAGE2_LOAD_BASE = 0x00100000
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self.STAGE1_STACK_SIZE = 0x00002000
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self.STAGE1_DATA_SIZE = 0x0000E000
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# Offset is relative to the temporary memory base 0xFEF00000
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self.STAGE1_STACK_BASE_OFFSET = 0x00080000 - (self.STAGE1_STACK_SIZE + self.STAGE1_DATA_SIZE)
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# To support large payload such as UEFI
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self.LOADER_RSVD_MEM_SIZE = 0x00B8C000
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self.PLD_RSVD_MEM_SIZE = 0x00500000
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self.PLD_HEAP_SIZE = 0x04000000
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self.FWUPDATE_SIZE = 0x00020000
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self.CFGDATA_SIZE = 0x00004000
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self.KEYHASH_SIZE = 0x00001000
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self.CFG_DATABASE_SIZE = self.CFGDATA_SIZE
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self.MRCDATA_SIZE = 0x00004000
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self.VARIABLE_SIZE = 0x00002000
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self.S3_DEBUG = 0
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self.SBLRSVD_SIZE = 0x00001000
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if len(self._PAYLOAD_NAME.split(';')) > 1:
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self.SPI_IAS1_SIZE = 0x00001000
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else:
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self.SPI_IAS1_SIZE = 0x00150000
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self._CFGDATA_INT_FILE = ['CfgData_Int_LeafHill.dlt']
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self._CFGDATA_EXT_FILE = ['CfgData_Ext_Gpmrb.dlt', 'CfgData_Ext_Up2.dlt','CfgData_Ext_OxbHill.dlt','CfgData_Ext_MB3.dlt','CfgData_Ext_JuniperHill.dlt']
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# If mulitple VBT table support is required, list them as:
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# {VbtImageId1 : VbtFileName1, VbtImageId2 : VbtFileName2, ...}
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# VbtImageId is ID to identify a VBT image. It is a UINT32 number to match
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# the ImageId field in the VBT container.
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# VbtFileName is the VBT file name. It needs to be located under platform
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# VbtBin folder.
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self._MULTI_VBT_FILE = {1:'Vbt.dat', 2:'Vbt_Up2.dat'}
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def GetPlatformDsc (self):
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dsc = {}
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common_libs = [
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'LoaderLib|Platform/$(BOARD_PKG_NAME)/Library/LoaderLib/LoaderLib.inf',
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'SerialPortLib|Silicon/$(SILICON_PKG_NAME)/Library/SerialPortLib/SerialPortLib.inf',
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'SocInfoLib|Silicon/$(SILICON_PKG_NAME)/Library/SocInfoLib/SocInfoLib.inf',
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'PlatformHookLib|Silicon/$(SILICON_PKG_NAME)/Library/PlatformHookLib/PlatformHookLib.inf',
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'ScSbiAccessLib|Silicon/$(SILICON_PKG_NAME)/Library/ScSbiAccessLib/ScSbiAccessLib.inf',
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'GpioLib|Silicon/$(SILICON_PKG_NAME)/Library/GpioLib/GpioLib.inf',
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'PchSpiLib|Silicon/CommonSocPkg/Library/PchSpiLib/PchSpiLib.inf',
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'SpiFlashLib|Silicon/CommonSocPkg/Library/SpiFlashLib/SpiFlashLib.inf',
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'IgdOpRegionLib|Silicon/CommonSocPkg/Library/IgdOpRegionLib/IgdOpRegionLib.inf',
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'IocIpcLib|Platform/$(BOARD_PKG_NAME)/Library/IocIpcLib/IocIpcLib.inf',
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'BootGuardLib|Silicon/$(SILICON_PKG_NAME)/Library/BootGuardLib20/BootGuardLib20.inf',
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'HeciLib|Silicon/CommonSocPkg/Library/HeciLib/HeciLib.inf',
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'MeChipsetLib|Silicon/ApollolakePkg/Library/MeChipsetLib/MeChipsetLib.inf',
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'PsdLib|Silicon/ApollolakePkg/Library/PsdLib/PsdLib.inf',
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'ShellExtensionLib|Platform/$(BOARD_PKG_NAME)/Library/ShellExtensionLib/ShellExtensionLib.inf',
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'BootMediaLib|Silicon/ApollolakePkg/Library/BootMediaLib/BootMediaLib.inf',
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'FlashDescriptorLib|Silicon/ApollolakePkg/Library/FlashDescriptorLib/FlashDescriptorLib.inf',
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'VtdLib|Silicon/$(SILICON_PKG_NAME)/Library/VtdLib/VtdLib.inf',
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'SmbusLib|Silicon/$(SILICON_PKG_NAME)/Library/SmbusLib/SmbusLib.inf',
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'HdaLib|Platform/$(BOARD_PKG_NAME)/Library/HdaLib/HdaLib.inf',
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'VtdPmrLib|Silicon/CommonSocPkg/Library/VtdPmrLib/VtdPmrLib.inf',
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'BaseIpcLib|Silicon/$(SILICON_PKG_NAME)/Library/BaseIpcLib/BaseIpcLib.inf',
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'TcoTimerLib|Silicon/CommonSocPkg/Library/TcoTimerLib/TcoTimerLib.inf',
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'TopSwapLib|Silicon/CommonSocPkg/Library/TopSwapLib/TopSwapLib.inf',
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'WatchDogTimerLib|Silicon/CommonSocPkg/Library/WatchDogTimerLib/WatchDogTimerLib.inf'
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]
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dsc['LibraryClasses.%s' % self.BUILD_ARCH] = common_libs
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return dsc
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def GetFlashMapList (self):
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img_list = self.GetImageLayout ()
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comp_list = []
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offset = 0
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# Skip Stitch_IPAD and Stitch_OPAD for flash map
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for img in img_list[2:][::-1]:
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child = img[1][0]
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if child[3] & STITCH_OPS.MODE_FILE_IGNOR:
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continue
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bname = os.path.splitext(child[0])[0]
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comp = {'name':child[0], 'bname':bname, 'offset':offset, 'size':child[2], 'flag': FLASH_MAP.FLASH_MAP_DESC_FLAGS['COMPRESSED'] if child[1] else 0}
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if bname in ['STAGE1A', 'STAGE1B', 'STAGE2', 'FWUPDATE', 'CFGDATA', 'MRCDATA', 'PAYLOAD', 'VARIABLE']:
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comp['flag'] |= FLASH_MAP.FLASH_MAP_DESC_FLAGS['REDUNDANT']
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else:
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comp['flag'] |= FLASH_MAP.FLASH_MAP_DESC_FLAGS['NON_REDUNDANT']
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comp_list.append (comp)
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offset += child[2]
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flag = FLASH_MAP.FLASH_MAP_DESC_FLAGS['REDUNDANT']
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comp_list.append ({'name':'SBLRSVD.bin','bname':'SBLRSVD','offset':0, 'size':self.SBLRSVD_SIZE, 'flag': FLASH_MAP.FLASH_MAP_DESC_FLAGS['NON_REDUNDANT']})
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comp_list.append ({'name':'BPM.bin', 'bname':'BPM', 'offset':0, 'size':0, 'flag': flag})
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return comp_list[::-1]
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def GetOutputImages (self):
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# define extra images that will be copied to output folder
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img_list = ['SlimBootloader.txt',
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'CfgDataStitch.py',
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'CfgDataDef.yaml',
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'CfgDataInt.bin'
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]
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return img_list
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def GetKeyHashList (self):
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# Define a set of new key used for different purposes
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# The key is either key id or public key PEM format or private key PEM format
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pub_key_list = [
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(
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# Key for verifying Config data blob
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HASH_USAGE['PUBKEY_CFG_DATA'],
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'KEY_ID_CFGDATA' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying firmware update
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HASH_USAGE['PUBKEY_FWU'],
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'KEY_ID_FIRMWAREUPDATE' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# Key for verifying container header
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HASH_USAGE['PUBKEY_CONT_DEF'],
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'KEY_ID_CONTAINER' + '_' + self._RSA_SIGN_TYPE
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),
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(
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# key for veryfying OS image.
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HASH_USAGE['PUBKEY_OS'],
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'KEY_ID_OS1_PUBLIC' + '_' + self._RSA_SIGN_TYPE
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),
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]
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return pub_key_list
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def GetImageLayout (self):
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ias1_flag = 0 if self.SPI_IAS1_SIZE > 0 else STITCH_OPS.MODE_FILE_IGNOR
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fwu_flag = 0 if self.ENABLE_FWU else STITCH_OPS.MODE_FILE_IGNOR
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img_list = []
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img_list.extend ([
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# Padding to ensure all other components in OBB partition will be aligned at 4KB boundary
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# 0xB00 assumes (IBBP.man, BPM.met) + (IPAD, IBBL, IBBM, OBB, FWUP, CFGD, PLD, VAR, MRCD) in BpdtIBB
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# 0x180 assumes (OPAD, PROV, EPLD) in BpdtOBB
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# If more files are added, the offset needs to be adjusted accordingly
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('Stitch_IPAD.bin', [
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('PADDING.bin', '', 0xB00, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_OPAD.bin', [
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('PADDING.bin', '', 0x180, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_FWU.bin', [
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('FWUPDATE.bin' , 'Lzma', self.FWUPDATE_SIZE, STITCH_OPS.MODE_FILE_PAD | fwu_flag, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_FB.bin', [
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('SPI_IAS1.bin', '', self.SPI_IAS1_SIZE, STITCH_OPS.MODE_FILE_PAD | ias1_flag, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_PLD.bin', [
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('PAYLOAD.bin', 'Lz4', self.PAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_VAR.bin', [
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('VARIABLE.bin', '', self.VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_MRCDATA.bin', [
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('MRCDATA.bin', '', self.MRCDATA_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_CFGDATA.bin', [
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('CFGDATA.bin', '', self.CFGDATA_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_KEYHASH.bin', [
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('KEYHASH.bin', '', self.KEYHASH_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_OBB.bin', [
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('STAGE2.fd', 'Lz4', self.STAGE2_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_IBBM.bin', [
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('STAGE1B.fd', 'Lz4', self.STAGE1B_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_IBBL.bin', [
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('STAGE1A.fd', '', self.STAGE1A_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_EPLD.bin', [
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('EPAYLOAD.bin', '', self.EPAYLOAD_SIZE, STITCH_OPS.MODE_FILE_PAD, STITCH_OPS.MODE_POS_TAIL)]
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),
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('Stitch_UVAR.bin', [
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('UEFIVARIABLE.bin', '', self.UEFI_VARIABLE_SIZE, STITCH_OPS.MODE_FILE_NOP, STITCH_OPS.MODE_POS_TAIL)],
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),
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])
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return img_list
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