This patch used the common API GetTimeStampFrequency() to get CPU
TSC frequency instead of the original GetCpuTscFreqency(). As part
of it, all SOC specific instances for GetCpuTscFreqency() were
removed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
- Add BistVal in STAGE1A_ASM_HOB structure
- Use MM0 register to preserve the BIST value
- Push BistVal while setup HOB in stack
- Add check for CPU BIST failure and halt the system when failed
Signed-off-by: Himanshu Sahdev aka CunningLearner sahdev.himan@gmail.com
By design, BootloaderCommonPkg should not refer to
BootloaderCorePkg. Hence removed those references in
the .inf files in Common pkg.
Moving SmbiosInitLib to Core pkg as it is a core feature.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Since HASH_INDEX_* is a 1:1 mapping with
COMP_TYPE_* we can remove HASH_INDEX_* and
replace with COMP_TYPE_*.
Also fix some misspellings.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch added a ContainerLib to support load and location a
component from a specified container. It copies the component
from flash to memory, authenticate it, and then decompress it if
required. It can also be used to support load component from flash
map in SBL stage2 or payload, such as payload or e-payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are cases where temporary memory is required in stages. Since
MemoryAllocationLib instance for stages has no de-allocation function,
it needs special handling. This patch added temporary memory management
into standard MemoryAllocatoinLib interface.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Restore the register information saved during the
normal boot, on S3 resume path for UEFI payload only.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Add ACPI_ENABLED() to align with MEASURED_BOOT_ENABLED().
Update MEASURED_BOOT_ENABLED() by checking PcdMeasuredBootEnabled
firstly.
Update PlatformFeaturesInit () in stage1b to fix potential inconsistent.
Update other code for changes above.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Some platform might need do some platform specific init
on all the threads. So add a MP hook using a PCD.
Np impact for the platform that doesn't need this hook.
This patch also enable InSMM bit for APL.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Removing the HOB defined by SBL to use generic HOBs from EDK2.
Update GraphicsLib for above HOB change.
Update osloader and multibootLib for hob change.
update APL and Qemu platform for hob change.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Smm bases for all the procs need to be relocated on the
S3 resume path (as payload is not run) for Windows boot.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch adds FPDT table into ACPI table, and updates all
the performance data for S3 path.
It also update basic boot performance data for reset end.
Other boot performance data could be updated by UEFI payload.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current SBL can only support on VBT file. However, different board
might need different VBT table. It is better to have the capability
to embed multiple VBT table into the image. This patch implemented
this feature and enabled it on QEMU. By default, it will take the
original behavior. if _MULTI_VBT_FILE in BoardConfig.py is specified,
multiple VBT files can be used.
If multiple VBT table support is required, list them as:
{VbtImageId1 :VbtFileName1, VbtImageId2 : VbtFileName2, ...}
VbtImageId is ID to identify a VBT image. It is a UINT32 number to
match the ImageId field in the VBT container.
VbtFileName is the VBT file name. It needs to be located under platform
VbtBin folder.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current code refers hash store as "key store". It is confusing
since there is no key stored in the image at all. Instead, the
public key hash is stored. The patch renames the KeyStore
to HashStore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Hardware Breakpoints must be used during CAR execution until
memory has been initiailzed for APL platform.
In order to use Hareware Breakpoints in UDK debugger, add
FlashRange in UDK config file and force to cover CAR area.
In SoftDebugger.ini of Windows UDK Debugger
Or In /etc/udkdebugger.conf of Linux UDK Debugger
[Target System]
FlashRange = 0xFEF00000:0x1100000
Additionally,
added Stage1BBase in STAGE1A_HOB
fixed Stage1A module base report
Change-Id: I717f87bf141168de0b0987eb309fd4c5d48d3c14
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Enable DebugAgentLib to support source level debug over serial
By default, source level debug is NOT enabled. ENABLE_SOURCE_DEBUG
needs to be set to 1 in BoardConfig.py of each Platforms.
- self.ENABLE_SOURCE_DEBUG = 1
As an initial drop, there are some limitations on APL platform.
- Stage1A does not include DebugAgentLib due to Stage1A size
limitation(32KB). Further optimization is required.
- DebugAgentLib supports ONLY POSTMEM debugging on APL currently.
Refer to EDKII Debugging:
- https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Debugging
- https://github.com/tianocore/tianocore.github.io/wiki/SourceLevelDebugPkg
Change-Id: Ia28c5470bc5755768f2b380cc1dabbcb8ee60f0d
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Additional changes for DebugAgent
- Adjust stage size depending on ENABLE_SOURCE_DEBUG Pcd value
- Add PeCoffFindAndReportImageInfo
- Fix debugger hang at Shell
Change-Id: I11b41e5ad610fcb2999e9d43e5dd8f8899e8265a
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Move PeCoffFindAndReportImageInfo() from LitePeCoffLib to DebugAgentLib
Change-Id: I2c4ab4f9561dfd0536da1820048f0e5f2660e2ab
Signed-off-by: Aiden Park <aiden.park@intel.com>
Maurice Ma