148c3d801d
feat: [ICX-D] FSP revision updated ( #2137 )
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FSP revision updated and aligned for MR4.
Tested to Boot Yocto.
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2024-02-09 08:12:28 -07:00
116e80a4b0
[ICXD][LCC][HCC] Update Microcode for both LCC and HCC
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Updated Microcode revision from 280 to 290
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2024-01-16 08:32:48 -07:00
c27857c458
[ICXD][LCC][HCC] Update Microcode for both LCC and HCC
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Update Microcode from 270 to 280
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2023-09-20 22:09:30 -07:00
372d75250c
[ICXD][LCC] Update Microcode for both LCC and HCC
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Update Microcode from 260 to 270
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2023-09-01 10:07:32 -07:00
3486563b6d
[ICXD][LCC] Update Microcode for both LCC and HCC
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Update Microcode from 230 to 260
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2023-08-31 10:16:17 -07:00
a278a87214
fix: [ICX-D] Fix Coverity issues
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Fixed Resource leak (CID 1229238)
Fixed Dereference null return value (CID 1515533)
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2023-08-09 09:18:38 -07:00
be4f1181dd
fix: [ICX-D] Fix Coverity issues ( #1979 )
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Fixed missing break in switch (CID 1444785)
Fixed Uninitialized scalar variable (CID 1444786)
Fixed Uninitialized scalar variable (CID 1444788)
Fixed Resource leak (CID 1229339
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2023-08-04 11:13:10 -07:00
f0b13a0941
[ICXD][LCC] Update Microcode for both LCC and HCC ( #1839 )
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Version update 1.1 to 1.2.
Update Microcode 201 to 230
Signed-off-by: cshur <cs.hur@intel.com>
2023-03-07 11:30:47 -07:00
13b0e6a266
ICXD: Fix R_CDF_PCH_GPIO_PCR_GPP_N_PADCFGLOCKTX register offset ( #1828 )
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Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
2023-02-06 12:44:06 -07:00
657acd2067
[ADL/RPL] Enhance PSD-related code ( #1822 )
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* Fix bound range exception thrown in HECI call for FW capabilities
Currently, whenever a HOB is not available containing FW
capabilities, a HECI call is made for the same. However,
whenever this HECI call is made, it throws a bound range
exception. This is because the ACK message struct used
has a data member but not a MKHI header member,
and the HECI call expects a struct with both members.
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
* Prioritize use of HOBs for population of PSD ACPI table
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
---------
Signed-off-by: Sean McGinn <sean.mcginn@intel.com>
2023-02-02 07:04:32 -08:00
65861c359c
ICXD: SGX: Added SGX launch control to SBL. ( #1771 )
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Added SgxLeWr and the hashes as configurable parameters in
sgxconfig.yaml.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2022-12-19 07:43:01 -08:00
d8ef36fbf7
feat: [ICX-D] FSP Update ( #1786 )
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FSP updated with the latest changes.
Tested to Boot Yocto.
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
Signed-off-by: Aakash Panwar <aakash.panwar@intel.com>
2022-12-15 08:09:48 -05:00
8a900cb414
Revert "ICXD: SGX: Added SGX launch control to SBL."
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This reverts commit 9fe47090c5
2022-11-14 10:13:01 -07:00
9fe47090c5
ICXD: SGX: Added SGX launch control to SBL.
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Added SgxLeWr and the hashes as configurable parameters in
sgxconfig.yaml.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2022-11-14 08:35:22 -07:00
91f39ba742
Revert "ICXD: SGX: Added SGX launch control to SBL."
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This reverts commit a7adcc2d5e
2022-11-07 19:42:50 -07:00
a7adcc2d5e
ICXD: SGX: Added SGX launch control to SBL.
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Added SgxLeWr and the hashes as configurable parameters in
sgxconfig.yaml.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2022-11-03 15:19:03 -07:00
94ab839eab
[ICXD] Upstream ICX-D LCC/HCC after PV
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Tested to boot Yocto and Windows.
Signed-off-by: cshur <cs.hur@intel.com>
2022-10-12 14:45:35 -07:00
Aakash Panwar