SerialPortLib sets UART Scratch Register to a known value at the first
initialization to avoid unnecessary re-initialization afterward. But,
one of Windows driver(SIO) re-configures UART Registers while the Scratch
Register is preserved. As a result, SBL skips serial port initialization
after restarting from Windows.
Therefore, force to initialize Serial Port at Stage1A all the time simply.
Signed-off-by: Aiden Park <aiden.park@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There is an issue with Vbt.bin in MR5; MR6 has this fixed.
Test: compiles OK, boots Linux OK.
Signed-off-by: Ursula Maplehurst <ursula@kangatronix.co.uk>
This patch adds IPC1 device to DSDT and exposes it to OS.
The behavior can be controlled by Config Data.
- Silicon Setting > Device Enable/Disable > Control 1 > IPC1 Enable/Disable
It also fixed#390.
Signed-off-by: Aiden Park <aiden.park@intel.com>
power button 4 second press will cause power button override
bit to set in PM1 status register, this bit is not cleared on
reset and is causing SMI storm during booting to OS.
Power button override bit if set is cleared now in stage1b and
this fixed the SMI storm issue.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch added csme wrapper driver for csme update library.
following functionality is added in this patch
1. Boardconfig PCD option ENABLE_CSME_UPDATE is added to
enable/disable csme update support
2. Boardconfig PCD option BUILD_CSME_UPDATE_DRIVER is added
to enable/disable building csme update driver
3. If BUILD_CSME_UPDATE_DRIVER is 1, user need to create
library that inludes csme update library
this newly created library will get linked to csme update
wrapper driver providing csme update driver
4. By default ENABLE_CSME_UPDATE is set to 0
5. Revision control for input and output data structure to
update driver is not implemented and will be avaiable
in further patches.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch allows APL and WHL(CFL) to use common header file for SPI
register access.
APL and CFL are using common SpiFlashLib and PchSpiLib, but Platform
code still refering to its own SPI registers header file.
- Remove duplicated header file
- Add common one to Silicon/CommonSocPkg
- Use SPI registers from common one in each Platform code
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch switched to use SerialPortLib in BootloaderCommonPkg for
QEMU and CFL platforms. For APL platform, it can also use this common
library. However, it has an optimized SerialPortLib with FIFO enabled.
So for APL, it still uses its SOC specific library.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch used the common API GetTimeStampFrequency() to get CPU
TSC frequency instead of the original GetCpuTscFreqency(). As part
of it, all SOC specific instances for GetCpuTscFreqency() were
removed.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
The WHL(and CFL-R) has its own SpiFlashLib, but it's almost identical
to common SpiFlashLib except of silicon specific part.
Therefore, CoffeelakePkg will have its own PchSpiLib and re-use common
SpiFlashLib.
- Remove CoffeelakePkg SpiFlashLib and related files
- Use commmon SpiFlashLib
- Use CoffeelakePkg SpiFlashLib
Signed-off-by: Aiden Park <aiden.park@intel.com>
QEMU has its own SpiFlashLib and SpiFlashLib.h file.
But, the header file is identical to the one in Silicon/CommonSocPkg.
Therefore, remove QEMU's one and re-use the common header file from
Silicon/CommonSocPkg.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Use common SpiFlashLib and PchSpiLib of Silicon/CommonSocPkg.
- No more use of SpiFlashLib from BootloaderCommonPkg
Signed-off-by: Aiden Park <aiden.park@intel.com>
Platform Device structure PLT_DEVICE supports both PCI and MMIO formats.
But, SpiConstructor gets SPI device info from Platform Device Table
and it always assumes the info as a PCI format. This patch is to support
both formats.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Remove Silicon specific part from SpiFlashLib and use separate
PchSpiLib for Silicon specific part
- Remove Silicon specific code from SpiFlashLib
- Use PchSpiLib for Silicon specific part
- Remove unnecessary ScSpiCommon.h file
Signed-off-by: Aiden Park <aiden.park@intel.com>
Most of PCH SPI controller are using same mechanism to access SPI BAR
and to control BiosWriteProtect by using SPI PCI device/function.
But, a certain Silicon may use different way to access them.
ex) SPI BAR from LPC A reg, BiosWriteProtect from LPC B reg
Split SpiFlashLib into two parts.
- SpiFlashLib for common part
- PchSpiLib for silicon dependent part
This patch is to prepare the split.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This is prerequisite step to clean-up SpiFlashLib.
- Copy from BootloaderCommonPkg to Silicon/CommonSocPkg.
No code change at all.
- Keep the existing BootloaderCommonPkg SpiFlashLib.
To avoid build failure on existing boards.
The existing boards will use new one at the final clean-up stage.
Signed-off-by: Aiden Park <aiden.park@intel.com>
On UP Xtreme board current code only supports PCH UART debug port.
But this board has two extra UART ports behind SIO chip F81801.
This patch added required initialization for the SIO chip to enable
UART on SIO. It can be enabled through platform data during stitching.
For exmaple,
"-p 0xAA000210" parameter in stitching will select PCH UART2.
"-p 0xAA00FF10" parameter will select SIO COM1 as debug device.
"-p 0xAA00FE10" parameter will select SIO COM2 as debug device.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Removing hard code in PrepareBuildComponentBin.py, so it could
support other platforms. And enhance its logic to support to
run in different places.
Moving repo and commit information to driver INF so this script
could reuse code to support different drivers.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This patch enabled very basic support to boot UP Xtreme (URL:
https://up-board.org/up-xtreme). Lots of porting are still required.
At this point, it can boot to OsLoader shell on PCH debug UART2 on
UP Xtreme board. It can also boot Ubuntu 18.04 and Yocto image.
Since there is no board ID check for UPX board, fixed Platform ID needs
to be specified during stitching. Here 0x10 is used for UPX Platform ID.
EX:
python Platform\CoffeelakeBoardPkg\Script\StitchLoader.py -i
XtremeBios.bin -s Outputs\cfl\SlimBootloader.bin -p 0xaa000210 -o ifwi.bin
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
S4 resume sets PWRBTN_EN. And since SCI_EN is set to 0,
this situation will generate spurious SMI# once GblSmi
is enabled.
Also moving RestoreS3regs before ProcessAllLocks, as SMI_LOCK
setting will prevent enabling GblSmi on S3 resume path.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Generate NHLT(Non HD audio Link Table) depending on CFGDATA
- Add HDA_CFG_DATA for HDA and NHLT
- Create NHLT depending on config data value
HdaLib is from edk2-platforms devel-IntelAtomProcessorE3900 branch.
- Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
- Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/
Include/Private/Library/DxeScHdaNhlt.h
Include/Private/Library/ScHdaLib.h
Include/Private/ScHdaEndpoints.h
Private/DxeScHdaLib/ScHdaEndpoints.c
Private/DxeScHdaLib/ScHdaLib.c
ScInit/Dxe/ScHda.c
Signed-off-by: Aiden Park <aiden.park@intel.com>
* [CFL] Fix typecasting bug in IsSgxFeatureCtrlSet()
Fix BOOLEAN typecasting bug in IsSgxFeatureCtrlSet() and add DEBUG_WARNs
when certain checks fail.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
* [CFL] Add microcode patch for CFL-S A stepping
Microcode patch for CFL-S A stepping was missing.
This was causing an issue with enabling Intel(R) SGX even when it was
enabled in the config. Hence, added the patch.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
This patch allows to use one GPIO pin to select different Payload ID.
When enabled, if GEN_CFG_DATA.PayloadId is set to 'AUTO', the GPIO pin
low level will select OsLoader payload, and high level will select UEFI
payload. If GEN_CFG_DATA.PayloadId is set to other values, the GPIO pin
low level will always select OsLoader payload, and high level will
select the Payload ID specified by GEN_CFG_DATA.PayloadId.
On APL LeafHill, OxbowHill and JuniperHill boards, the current GPIO is
set to GP48 (Pin 10 on J6B2 connector). This GPIO pin should be used as
input signal, and can be reconfigured for alternative functions after
the Payload ID selection is done.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Necessary FSP header files(ex. Fsp*Upd.h) will be copied from FSP
release repo. Additionally, cfl target for WHL/CFL platforms will
verify minimum FSP version like apl target.
Signed-off-by: Aiden Park <aiden.park@intel.com>
On WHL, if using Boot Guard profile 0, booting from BP1 will be
significantly slower than BP0. It is because some code region in BP1
is not covered by MTRR cache settings. This patch adjusted MTRR
settings during PostTempRamInit notification to cover full flash
code region if Boot Guard profile 0 is used.
It fixed#188.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch utilizes information from FspBin.inf to checkout specific
tag from FSP repo and copy files to SBL source tree.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Cleaned up SpiFlashLib in APL platform, and move it into
BootloaderCommonPkg, so that other platform could reuse
this SpiFlashLib
Signed-off-by: Guo Dong <guo.dong@intel.com>
Add ACPI_ENABLED() to align with MEASURED_BOOT_ENABLED().
Update MEASURED_BOOT_ENABLED() by checking PcdMeasuredBootEnabled
firstly.
Update PlatformFeaturesInit () in stage1b to fix potential inconsistent.
Update other code for changes above.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Common MM_PCI_ADDRESS() provided PCI device BDF to PCIE MMIO base address.
So remove MmPciAddress() and MmPciBase () defined in platform and update
code to use MM_PCI_ADDRESS().
Add TO_PCI_LIB_ADDRESS() in common library.
Signed-off-by: Guo Dong <guo.dong@intel.com>
FileSystemLib provides generic interfaces to access file system and
its files as a abstraction of FatLib/ExtLib.
- Added CloseFileSystem
If there are opened files in a specific filesystem, those files
will be de-allocated in CloseFileSystem.
- Added OpenFile/GetFileSize/ReadFile/CloseFile
The ReadFile() does not allocate any memory for the file content.
The caller of OpenFile() MUST allocate necessary memory before
calling ReadFile().
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch will add support for updating multiple firmwares
using a single capsule image.
Following modifications are made for existing firmware update flow
1) Gather and validate capsule image
2) State Machine will be set to capsule processing state.
3) Signature of the capsule image is now stored in reserved region
During each reboot until the end of firmware update, stored signature
will be compared against the capsule image signature to make sure
capsule image is not modified until the end of firmware update.
4) Process Capsule image to gather firmware images
5) Each Firmware image information will be stored in reserved region
using FW_UPDATE_COMP_STATUS. Update pending will be marked to
update pending state indicating that this image is not processed.
6) Firmware update will use the reserved region comp structures starting
with the first image with update pending state, update the comp update
pending field to processing and applies the image. After the update, pending
field will be updated to Done and updates the status of the update in the
component structure and moves on to next image found.
7) After all the component structure in the reserved region updating pending
field are set to Done. Firmware update mode is exited.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Firmware update with latest code broke on APL platform.
This patch fixed#162 by:
- Corrected the HECI command response flag check
- Always read FWU state machine using SPI command instead memory map
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For APL, the board might need SMBUS communication to talk to some
devices, such as PMIC. This patch ported the SMBUS library from
open sourced EDK2 Minnowboard3. Basic test was done on LeafHill
CRB to read/write PMIC registers through SMBUS.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch fixed some QEMU firmware update related issues.
It enabled firmware update testing on QEMU using script.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added SMM TSEG range support in QEMU FSP. It also added
QEMU TSEG base and size reporting in HOB.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Build a new SMM info HOB to payload to report SMM info.
Add UEFI payload variable region into flash map.
TEST=Tested on LeafHill with UEFI payload.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Ported the patch from EDKII repository and added following up changes
<Original commit info in EDKII>
commit 7b500c606ad101fad52327318af37889048cd45e
Author: Liming Gao <liming.gao@intel.com>
Date: Tue Oct 16 23:08:46 2018 +0800
BaseTools: Remove the step to freeze python tool
https://bugzilla.tianocore.org/show_bug.cgi?id=1257
Binary python tool is not supported anymore. So, the freeze python tool
step is not required.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch updates firmware update code to get capsule location
information from configuration data instead of searching in all the
available boot media.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Current code refers hash store as "key store". It is confusing
since there is no key stored in the image at all. Instead, the
public key hash is stored. The patch renames the KeyStore
to HashStore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Rename VTd to Vtd including directories, files and variables to follow
EDKII coding convention.
Change-Id: I0c88dcc1087eafcefb4f6d99dcd25e7b3d031a71
Signed-off-by: Aiden Park <aiden.park@intel.com>
Root-cause is Special characters (comma) exist in the header file.
Silicon\ApollolakePkg\Include\Library/HeciLib.h: warning C4819: The file contains a character that cannot be represented in the current code page (950). Save the file in Unicode format to prevent data loss
Aiden Park