Migrated to Azure Pipelines for SBL CI to align with EDK2 project.
This is an initial commit to enable basic check. Currently it will
verify patch format and QEMU GCC build and test.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added support to launch payload module on top of OsLoader.
Comparing with payload binary, payload module will utilize the API
services provided by OsLoader, so it will have smaller size. Other
than this, the concept is exactly same as normal payload. For payload
module, additional parameter is required to pass into the payload
module entry point.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch added vbt.bsf and vbt.bat for coffeelake. Opensourced
vbt from github does not support DP port, newly added
vbt supports DP.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This an initial patch to add x64 build for SBL. A new build flag
'-x64' is added to indicate x64 arch build. This cannot be fully
used at this moment because it has many dependencies on other x64
libraries. Only VTF reset vector x64 build is tested.
VTF x64 flow is different from IA32. It switches to 32 bit
mode as usual and then calls into FspTempRamInit to set up CAR.
Once CAR is ready, it builds 4GB identical mapping page table for
x64 and then switches to x64 long mode. Finally, it locates the
STAGE1A entry point and tranfers the control to STAGE1A in pure
64 bit mode.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
Necessary FSP header files(ex. Fsp*Upd.h) will be copied from FSP
release repo. Additionally, cfl target for WHL/CFL platforms will
verify minimum FSP version like apl target.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch utilizes information from FspBin.inf to checkout specific
tag from FSP repo and copy files to SBL source tree.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Maurice Ma