Fix unresolved external and type-cast issues for X64 build.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Co-authored-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This will create a HOB for PCI Root Bridge Resource information.
The PciRootBridgeInfo Hob can be used to update resource ranges of multiple
root bridges in platform PCI tree ASL.
A payload can also use this info to skip duplicated root bridge scan.
Signed-off-by: Aiden Park <aiden.park@intel.com>
In certain condition, the FspTempRamExit() API will be executed from
CAR. If so, the thunk call itself cannot be in CAR otherwise the
call will hang immediately after the CAR teardown. To resolve it,
the thunk call needs to be copied over to memory before calling the
FspTempRamExit() API. This patch implemented this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable Stage1A boot in X64 mode
This patch added necessary changes to enable QEMU boot through
Stage1A in SBL X64 build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable QEMU Linux boot in X64 mode
This patch enabled SBL X64 boot for Linux. At this moment, since
FSP is still in 32 bit mode, it is required to thunk back into
32 bit mode to call FSP APIs.
It fixed#622.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Due to missing normal function implementations in some x64 code, GCC
optimized many code off from the final image which caused synbol
patching issue later on. This patch fixed this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Add missing X64 MdePkg Library
This adds some missing Library from EDKII Stable201911.
- MdePkg/Library/BaseMemoryLibRepStr/X64
- MdePkg/Library/BaseSynchronizationLib/X64
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Make X64 target buildable
This is just to build X64 target - Not functional.
Signed-off-by: Aiden Park <aiden.park@intel.com>
There are lots of common code in Stage1A/1B/2, so it makes sense
to put those into a StageLib so that the same code can be reused.
As part of it, PagingLib is also restructured to align with Stage
mapping/remapping. It will consider both X64 mode and IA32 mode.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added DMA memory type into memory allocation pool for payloads.
This DMA memory buffer with PcdDmaBufferSize is located at address
aligned at PcdDmaBufferAlignment after Payload reserved memory. Memory
type EfiRuntimeServicesData is used to indicate DMA memory type.
Stage1B calculates the DMA memory location using fixed PCDs so that
platform can set up DMA protection as early as possible after memory is
ready. In Stage1B or Stage2 platform code should use platform VTd
information to setup PMR to protect all low memory except for the DMA
buffer range. DMA memory will be added into memory pool at the entry
point of the payload. Before transfering to OS, the DMA memory protection
can be disabled, and the DMA memory pool can be reclaimed for OS usage.
Currently only boot media device will utilize the DMA buffer range for
block access operations. So it should only be required by payloads. GFX,
when enabled, will also use DMA. It will be targeted to the system stolen
memory which is not protected by PMR.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For non UEFI boot, it is required to put an SMBIOS entry in legacy F
segment at 16-byte aligned boundary so that OS can locate the SMBIOS
by searching the region. This patch added this logic to add SMBIOS
entry at fixed location 0xFFF60. ACPI table has the similar legacy
root pointer at fixed location 0xFFF80.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL PCI enumeration code will zero out all PCI command registers and
PCI bridge control registers. However, FSP might have programmed some
of the registers already, and some of the bits are expected to be
preserved through the PCI enumeration. This patch addressed this issue
by only clearing the bits that are required during the PCI enumeration.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
PciEnumeration() scans a single PCI root bridge currently.
The PCI_ENUM_POLICY_INFO structure will be generated at build time,
and this will allow PCI enumeration more flexible.
typedef struct {
UINT8 DowngradeIo32;// default:1
UINT8 DowngradeMem64; // default:1
UINT8 DowngradePMem64;// default:1
UINT8 Reserved;
UINT8 BusScanType; // default:0 (0: list, 1: range)
UINT8 NumOfBus; // the number of BusScanItems
UINT8 BusScanItems[0];
} PCI_ENUM_POLICY_INFO;
Signed-off-by: Aiden Park <aiden.park@intel.com>
FPDT size should be FIRMWARE_PERFORMANCE_TABLE. And updated
this logic to correct the size and adjust next ACPI table
starting address.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This will allow OsLoader payload to boot to 64-bit kernel entry point.
If CPU supports 64-bit mode and a kernel image has 64-bit entry point,
OsLoader will switch to 64-bit long mode and jump to the 64-bit entry
point. Otherwise, continue to boot to 32-bit entry point.
- Ported necessary code from EDK2 VitualMemory.c in MdeModulePkg
- Moved PagingLib from BootloaderCorePkg to BootloaderCommonPkg
- Removed unused FlushCacheLine
- TBD: 64-bit IDT
Next step is to support 64-bit Payload.
- 32-bit compatible mode
- 64-bit CryptoLib
- etc.
Signed-off-by: Aiden Park <aiden.park@intel.com>
In order to sync up with EDK201911 stable release, it is required
to add missing header files in the INF file. Otherwise, the build
will throw warnings. This patch added the missing headers in INF
files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled Visual Studio 2017 Community 2017 build support.
The following were done:
- Added new method to detect VS2017 installation path and version
- Droped VS2005, VS2008, VS2010 and VS2012 build support. Only
VS2013 and VS2015 are supported.
- Fixed build issue in FspApiLib due to new compiler optimizations
- Synced the build support for QEMU FSP patch
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
CSME driver is not a component rather it is a driver to
update CSME binary, so it is not required to update status
of the driver to FWST ACPI table.
As part of the above change, gCsmeFWUDriverImageFileGuid is
moved from PayloadPkg.dec to bootloadercommonpkg.dec
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch did some of the following clean up:
- Rename *_HOB to *_PARAM for Stage1A/Stage1B/Stage2.
This is to avoid confusion between real HOB and the parameter
data block passed through stages.
- Rename BistVal to CpuBist.
This is to make it more clear.
- Add BUF_INFO definition.
BUF_INFO will be used as a general structure.
- Remove CarBase/Top in Stage1B HOB
They are not used at all.
- Clean memory allocation in Stage1A
Restructured the buffer allocations for Stage1A global
data so that it is easier to read and maintain.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch moved some library APIs into BootloaderCommonLib, including
GetComponentInfo() and GetComponentHash().
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
HASH_STORE_TABLE is updated and HASH_STORE_DATA is added
to provide info with variable length sizes. Usage bits would
notify for multiple component/key using the same hash.
These data structure would optimize the hash store size
in storage.
PcdHashStoreSize would define the size of Hash store
to allocate in bios bootup.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
Component Hash is passed with TpmExtendHash if available.
Hash Store is getting optimized on storage and this would avoid
setting component hash in hash table. SetComponent Hash API is
removed in bootloaderlib.
Added HashAlg param to TpmExtendHash for future purposes
where TPM PCR bank would be selected based on HashAlg.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
EnableAvx ASM is included as part ExtraLibs.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL does not check the FSP Notify API return status. As a
result, if reset is requested, it is ignored by SBL. This patch
added FSP reset request check for FspMemoryInit, FspSiliconInit and
FspNotifyPhase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This provides basic insertion sort API for Linked List. As part of change,
this insertion sort is used for PCI BAR calculation by its alignment
and for shell commands list by its name.
Signed-off-by: Aiden Park <aiden.park@intel.com>
There are multiple instances of sorting use case in SBL. For example,
memory map sorting and CPU APIC ID sorting. This patch added a generic
quick sort library to provide common sort API. As part of the change,
the quick sort API will be used for memory map and CPU APIC ID sorting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch sorts the CPU info entry according to their thread distances.
It is required to list CPU thread with furthest distance first in MADT
so as to better utilize CPU resources.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
If FPDT->Length is just the size of FIRMWARE_PERFORMANCE_TABLE,
BOOT_PERFORMANCE_TABLE and S3_PERFORMANCE_TABLE are overwritten
by the next Table in ACPI init. Therefore, make the size in the
header as sizeof(INTERNAL_FIRMWARE_PERFORMANCE_TABLE) so that
the next table starts after INTERNAL_FIRMWARE_PERFORMANCE_TABLE.
Otherwise, S3 Perf Table can't be located on S3 resume path.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Error: conversion from 'UINT32' to 'UINT8', possible loss of data
MADT ProcessorId and ApicId has the size of UINT8. Cast the size from UINT32 to UINT8.
Change-Id: I3f46b2015b0d21c2b3e2f9389ecb8d5364ed5a5e
Signed-off-by: Aiden Park <aiden.park@intel.com>
Currently, the common hook UpdateMadt() was updating fixed size of
ProcessorLocalApic entries.
This allows the hook to append ProcessorLocalApic entries with the number
of detected CPUs in runtime.
Signed-off-by: Aiden Park <aiden.park@intel.com>
To make PlatformUpdateAcpiTable() hook its contents and length easily,
allocate a memory from low to high and appends each tables to higher direction
Signed-off-by: Aiden Park <aiden.park@intel.com>
By design, BootloaderCommonPkg should not refer to
BootloaderCorePkg. Hence removed those references in
the .inf files in Common pkg.
Moving SmbiosInitLib to Core pkg as it is a core feature.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Since HASH_INDEX_* is a 1:1 mapping with
COMP_TYPE_* we can remove HASH_INDEX_* and
replace with COMP_TYPE_*.
Also fix some misspellings.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch added a ContainerLib to support load and location a
component from a specified container. It copies the component
from flash to memory, authenticate it, and then decompress it if
required. It can also be used to support load component from flash
map in SBL stage2 or payload, such as payload or e-payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are cases where temporary memory is required in stages. Since
MemoryAllocationLib instance for stages has no de-allocation function,
it needs special handling. This patch added temporary memory management
into standard MemoryAllocatoinLib interface.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SmmBase Info should not be expected by MpInit if the
platform/payload has not updated the Tseg region.
Check for the COMM signature before proceeding to Rebase.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Restore the register information saved during the
normal boot, on S3 resume path for UEFI payload only.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Synced up MdePkg, IntelFsp2Pkg and BaseTools to EDK2 stable tag
edk2-stable201905.
There are several changes for MdePkg and BaseTools.
MdePkg:
- Support light print to reduce SBL size
MdePkg\Library\BasePrintLib\PrintLibInternal.c
MdePkg\Include\Library\DebugLib.h
- TCG TPM2 spec changes and remove dependencies
MdePkg\Include\IndustryStandard\UefiTcgPlatform.h
MdePkg\Include\IndustryStandard\Tpm2Acpi.h
- Use old NVM protocol file
MdePkg\Include\Protocol\NvmExpressPassthru.h
- Removed unused files
BaseTools:
- Added LZ4 support
- Removed unused files
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
stalamudupula