SBL only support ELF type: EXEC (Executable file)
This changes also allow loading ELF type: DYN (Shared object file)
This is required to boot recent ACRN Hypervisor.
Signed-off-by: Markus Schuetterle <markus.schuetterle@intel.com>
There are cases where temporary memory is required in stages. Since
MemoryAllocationLib instance for stages has no de-allocation function,
it needs special handling. This patch added temporary memory management
into standard MemoryAllocatoinLib interface.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When writing flash in SMM mode, some platform need disable SMM write
protection. when this flag is set, it means this platform need disable
SMM write protection.
Signed-off-by: Guo Dong <guo.dong@intel.com>
SmmBase Info should not be expected by MpInit if the
platform/payload has not updated the Tseg region.
Check for the COMM signature before proceeding to Rebase.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Restore the register information saved during the
normal boot, on S3 resume path for UEFI payload only.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
There may be additional cmd line params specified
by a platform that needs to be added without
updating the IAS image cmd line data. These
optional additional cmd line params can be included
via CFG data, Shell command, etc., and applied
by setting the mAppendCmdLineParams pointer.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Currently there is some limitation with mounting an
EXT4 partition to retrieve a file for booting when
the partition was not properly umounted during the
previous usage (ex. powering off an OS without
using 'poweroff' command, unplugging power, etc.).
There is no recovery support in the Ext23Lib but
as a temporary solution we can ignore the recovery
bit to avoid boot issues when the recovery bit is
flipped due to unexpected power loss.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
When loading a Linux kernel we should not
limit the size of the kernel being loaded
to 15MB but we should verify that the kernel
will not overwrite the payload which can
some times be located in low memory where
the kernel is being loaded.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
- Revert 'Determine Firmware Update boot mode at post tempram exit #210'
- Enable SMI on S3 resume path ONLY with UEFI payload
- Move EnableSmi from PrePciEnumeration to EndOfFirmware
Signed-off-by: Aiden Park <aiden.park@intel.com>
Same GpioPinOption is used in PID selection and Payload selection.
Re-use GpioPinOption in PIDGPIO_TMPL template as well.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This issue happens when a template file includes another files
since template dictionary has '!include' line itself instead of
its contents.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Config data should offer a full list of GPIOs for the
end-user to be able to select for PlatformID.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Generate NHLT(Non HD audio Link Table) depending on CFGDATA
- Add HDA_CFG_DATA for HDA and NHLT
- Create NHLT depending on config data value
HdaLib is from edk2-platforms devel-IntelAtomProcessorE3900 branch.
- Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c
- Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/
Include/Private/Library/DxeScHdaNhlt.h
Include/Private/Library/ScHdaLib.h
Include/Private/ScHdaEndpoints.h
Private/DxeScHdaLib/ScHdaEndpoints.c
Private/DxeScHdaLib/ScHdaLib.c
ScInit/Dxe/ScHda.c
Signed-off-by: Aiden Park <aiden.park@intel.com>
Issue:
The Bios.xml generated from StitchIfwi.py is referring to Stitch_PROV.bin.
But the SBL Output Stitch_Components.zip contain instead Stitch_FB.bin.
Fix for issue #224:
Consistently use input file names for IFWI stitching, by chosen for 'FB'
instead of 'PROV'.
Signed-off-by: Markus Schuetterle <markus.schuetterle@intel.com>
Move Intel(R) SGX library to CommonBoardPkg, except for the config.
This is because Intel(R) SGX library is common for all platforms that
support Intel(R) SGX (Intel(R) SGX is available on all platforms
starting 6th generation Skylake).
Config is specific to each platform since options can vary from platform
to platform.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
* [CFL] Fix typecasting bug in IsSgxFeatureCtrlSet()
Fix BOOLEAN typecasting bug in IsSgxFeatureCtrlSet() and add DEBUG_WARNs
when certain checks fail.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
* [CFL] Add microcode patch for CFL-S A stepping
Microcode patch for CFL-S A stepping was missing.
This was causing an issue with enabling Intel(R) SGX even when it was
enabled in the config. Hence, added the patch.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
Remove the requirement for the end user to know
community, group etc. And just expose GPIO pins
to select to program PlatformID.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Below items have been changed.
- Capsule device instance index from 5(range 0-3) to 0
- Set default value for PCIE RP Power/Reset pin even if it's disabled
- Maximum GPIO alternative mode number from 3 to 5.
It fixed#204.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Currently, pcie clock configuration has fixed values while updating
FSP-S UPDs.
Added a capability to use PCIE CFGDATA for pcie clock configuration.
Additionally, PCIE config page/sub-pages hierarchy has been updated.
Old: Silicon Settings
- PCIE RP Config Data
New: Silicon Settings
- PCIE Config
- PCIE RP Config
- PCIE Clock Config
Signed-off-by: Aiden Park <aiden.park@intel.com>
The PCIe Root Port utilization for GP MRB is:
RP0 - /
RP1 - /
RP2 - CFB I210
RP3 - CFB M2 Cellular
RP4 - I210
RP5 - BT/WIFI
CFB = Customer Feature Board
Issue:
PCIe device BT/WIFI was not enumerated.
This corrects the complete PCIE_RP_CFG_DATA configuration
for the GP MRB board.
Signed-off-by: Markus Schuetterle <markus.schuetterle@intel.com>
If the platform provides an empty or a NULL string,
Smbios type might end abruptly and the Types are
reported incorrectly.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
ConfigEditor returns a warning in GPU Config page.
WARNING: Value '2' is an invalid option for 'InternalGfx' !
Update InternalGfx from 0x02 to 0x01 !
The InternalGfx does not provide proper options and its default value
must be '1' or '0' instead of '2'.
Additionally, renamed 'GPU Config' page name to 'Graphic and Display'
and also removed unnecessary sub-page 'GPU'.
Signed-off-by: Aiden Park <aiden.park@intel.com>
EC_SMI_N GPIO pin is currently not being used by Slim Bootloader.
But configuring this will cause spurious SMIs to occur when EOS
is set in the payload.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Current default GPIO payload ID selection is UEFI on APL platform
since the GPIO pin is high without any jumper set. This patch
changed the default paylod ID to OsLoader when the GPIO is set to
high.
It fixed#208.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows platform to use BoardConfig.py to override the
LOGO_FILE path so that customized logo file can be used instead of
the common one.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There is a invalid value(8MB) in CfgData_Memory.dsc which causes
an WARNING when opening memory setting in ConfigEditor.
WARNING: Value "8388608" is an invalid option for "TsegSize" !
Update TsegSize from 0x00800000 to 0x01000000 !
In FspmUpd.h description, Tseg Size is "0x400000 for Release build
and 0x1000000 for Debug build".
Tseg size 4MB(0x400000) is enough with SBL regardless of build type.
Therefore, let's remove config option and use fixed size(4MB) simply.
It fixed#205.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Whiskeylake platform contains memory SPD data in memory configurations.
Since it has 4 SPD tables, loading is very slow in ConfigEditor. The SPD
table can be broken down into individual page for display to enhance the
loading performance in ConfigEditor.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows to use one GPIO pin to select different Payload ID.
When enabled, if GEN_CFG_DATA.PayloadId is set to 'AUTO', the GPIO pin
low level will select OsLoader payload, and high level will select UEFI
payload. If GEN_CFG_DATA.PayloadId is set to other values, the GPIO pin
low level will always select OsLoader payload, and high level will
select the Payload ID specified by GEN_CFG_DATA.PayloadId.
On APL LeafHill, OxbowHill and JuniperHill boards, the current GPIO is
set to GP48 (Pin 10 on J6B2 connector). This GPIO pin should be used as
input signal, and can be reconfigured for alternative functions after
the Payload ID selection is done.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In ConfigEditor, when open DSC files, many files will show up. It
is expected to only open the CfgDataDef.dsc. This patch changed
the file match pattern to only list *Def.dsc file. In this way,
user will not make mistake to open some include DSC file.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch allows payload ID selection toggling using GPIO. When
the payload ID is set to "AUTO" in CFGDATA, the actual payload ID
will be updated according to current GPIO level. If the GPIO is low,
the payload ID will be set to 0 to boot OsLoader/FwUpdate payload.
If the GPIO is high, the payload ID will be set to 'UEFI' to boot
UEFI payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When SBL calls board notification ReadyToBoot and EndOfFirmware in
Stage2, OsLoader will assert on APL platform. It was caused by NULL
pointer access in ClearFspHob(). This patch added NULL pointer check
before zeroing out memory. It fixed#197.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When determining which extent node to fetch
the filesystem block address from for a file's
data we should count from block 0 of the file
and when we enter into a non-zero extent node
we need to subtract the starting block number
from the file block number we are looking for
so that we don't skip over any blocks.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
The previous implementation has a little confusion in license header.
To avoid further annoying, simply re-implement ElfLib.
- 32bits, little-endian, executable elf only supported
- elf32.h/elf_common.h from BaseTools/Source/C/GenFw
- LoadElfImage() interface changed
Signed-off-by: Aiden Park <aiden.park@intel.com>
The current EXT2/3 library does not support EXT4 partition
reading namely due to a limitation with handling extents
instead of block maps within an I_node's I_block data.
There is a todo currently to support 48-bit logical block
addressing, the code currently does not support reading
larger than 32-bit addresses; throw an ASSERT if upper
16-bits are non-zero.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Previous commit 4061d47f30 missed one
condition while handling the board notification calls. For built-in
payload such as OsLoader and FwUpdate, it will issue notifications
from payload through SBL platform services. So for these payloads,
board notification should not be called in SBL Stage2. This patch
fixed this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current SBL does not call board ReadyToBoot & EndOfFirmware phases
in Stage on normal boot flow. Current open source UEFI payload does not
do it either. It caused some security concerns. The patch enforced
these notification calls on normal boot flow in SBL for all payloads
except for those that can handle board and FSP notification on its own.
It fixed#191.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Change DEBUG_ERROR to DEBUG_INFO for reporting UpdateFspmSgxConfig() and
UpdateFspsSgxConfig() return statuses since failing to update FSP
variables for Intel(R) SGX is not necessarily due to an error.
Signed-off-by: Iyer, Naveen <naveen.iyer@intel.com>
Necessary FSP header files(ex. Fsp*Upd.h) will be copied from FSP
release repo. Additionally, cfl target for WHL/CFL platforms will
verify minimum FSP version like apl target.
Signed-off-by: Aiden Park <aiden.park@intel.com>
On WHL, if using Boot Guard profile 0, booting from BP1 will be
significantly slower than BP0. It is because some code region in BP1
is not covered by MTRR cache settings. This patch adjusted MTRR
settings during PostTempRamInit notification to cover full flash
code region if Boot Guard profile 0 is used.
It fixed#188.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch utilizes information from FspBin.inf to checkout specific
tag from FSP repo and copy files to SBL source tree.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
In current FAT lib, the file path matching code will just compare
the 1st N chars and ignored the remaining. The end of the string
should be checked to ensure exact matching. As part of this fix,
the GRUB config parsing library needs to be updated since the file
name length field is one less than expected.
It fixed#183.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Synced up MdePkg, IntelFsp2Pkg and BaseTools to EDK2 stable tag
edk2-stable201905.
There are several changes for MdePkg and BaseTools.
MdePkg:
- Support light print to reduce SBL size
MdePkg\Library\BasePrintLib\PrintLibInternal.c
MdePkg\Include\Library\DebugLib.h
- TCG TPM2 spec changes and remove dependencies
MdePkg\Include\IndustryStandard\UefiTcgPlatform.h
MdePkg\Include\IndustryStandard\Tpm2Acpi.h
- Use old NVM protocol file
MdePkg\Include\Protocol\NvmExpressPassthru.h
- Removed unused files
BaseTools:
- Added LZ4 support
- Removed unused files
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Markus Schuetterle