At PciScanBus, a PCI bridge sets PCI Bridge Subordinate Bus to 0xFF
temporary to go thru any PPB. But, a platform has some reserved buses
(ex. 0xFB-0xFF) on PCI hierarchy, and writing 0xFF regardless of
reserved bus ranges causes system hang.
Therefore, PciGetMaxBusNumber will be used for PCI Bridge Subordinate
Bus and it gets the number of buses from PCI Enum Policy to skip the
reserved buses.
Signed-off-by: Aiden Park <aiden.park@intel.com>
FspsUpd variable made global so that it could be accessed out of
FspSilicon function.
Patchable PCD has been created for FspsUpd and Memory pool allocated.
Signed-off-by: Perni <ramesh.chandra.perni@intel.com>
- Default SMBIOS Table initialized when SMBIOS is enabled.
- If required, Every Platform can override platform specific information.
- Enable SMBIOS in Qemu platform.
- Update Memory allocation for SmbiosStringsPtr for 32 entries.
Signed-off-by: Sm NARAYANAN <s.m.narayanan@intel.com>
FSP 2.1 introduced new requirement to use bootloader stack for FSP-M. It
will cause issue for SBL since SBL only uses a small stack in Stage1. To
address this issue, a new PCD PcdFSPMStackTop is added to control the
stack settings for FSP-M.
- If it is 0, it will not switch stack before calling FspMemoryInit API.
- If it is 0xffffffff, it will switch to the new default FSP stack
before calling FspMemoryInit API.
- For other values, it will switch to the new stack at specified value
before calling FspMemoryInit API.
This PCD will be set automatically by FSP_M_STACK_TOP variable in
BoardConfig.py file.
This code has been tested on UP Extreme board with latest FSP version.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This will support PCI SR-IOV(Single Root I/O Virtualization).
- Controlled by PcdSrIovSupport (SUPPORT_SR_IOV in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch will generate a SW smi on S3 resume path when using
UEFI payload. Handler for this Sw smi in UEFI payload will
program SMRR base and mask for BSP and all AP's.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This will enable ARI(Alternative Routing-ID Interpretation).
- Controlled by PcdAriSupport (SUPPORT_ARI in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch enhances MapMemoryRegion subroutine to
add PDP entries for mapping addresses > 4GiB.
Only 1:1 mapping is provided for Above4Gb addresses.
And linear addresses are mapped to 1GiB pages.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This will support S3 resume path on X64 thru 16-bit waking vector.
- Port WakeUp code from EDKII
- Remove duplicated calls of FindS3Info from CpuInit
- Verified with Yocto on a WHL board
- TBD: 64-bit waking vector with supported OS
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will fix MpInit failure on X64 build.
The ApFunc() gets invalid parameters due to mismatched calling convention.
- Add EFIAPI to match calling convention
This can be verified with '-smp' option on QEMU target.
qemu-system-x86_64
-machine q35 -m 256 -nographic -serial mon:stdio
-pflash Outputs/qemu/SlimBootloader.bin
-smp 255
Signed-off-by: Aiden Park <aiden.park@intel.com>
Correct the index reported while dumping the
PCI resource information.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Co-authored-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Fix unresolved external and type-cast issues for X64 build.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Co-authored-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This will create a HOB for PCI Root Bridge Resource information.
The PciRootBridgeInfo Hob can be used to update resource ranges of multiple
root bridges in platform PCI tree ASL.
A payload can also use this info to skip duplicated root bridge scan.
Signed-off-by: Aiden Park <aiden.park@intel.com>
In certain condition, the FspTempRamExit() API will be executed from
CAR. If so, the thunk call itself cannot be in CAR otherwise the
call will hang immediately after the CAR teardown. To resolve it,
the thunk call needs to be copied over to memory before calling the
FspTempRamExit() API. This patch implemented this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable Stage1A boot in X64 mode
This patch added necessary changes to enable QEMU boot through
Stage1A in SBL X64 build.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* [QEMU] Enable QEMU Linux boot in X64 mode
This patch enabled SBL X64 boot for Linux. At this moment, since
FSP is still in 32 bit mode, it is required to thunk back into
32 bit mode to call FSP APIs.
It fixed#622.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Due to missing normal function implementations in some x64 code, GCC
optimized many code off from the final image which caused synbol
patching issue later on. This patch fixed this.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Add missing X64 MdePkg Library
This adds some missing Library from EDKII Stable201911.
- MdePkg/Library/BaseMemoryLibRepStr/X64
- MdePkg/Library/BaseSynchronizationLib/X64
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Make X64 target buildable
This is just to build X64 target - Not functional.
Signed-off-by: Aiden Park <aiden.park@intel.com>
There are lots of common code in Stage1A/1B/2, so it makes sense
to put those into a StageLib so that the same code can be reused.
As part of it, PagingLib is also restructured to align with Stage
mapping/remapping. It will consider both X64 mode and IA32 mode.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Visual Studio reports more pointer type cast errors with 64-bit build.
This will cover the issue on the existing targets.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch added DMA memory type into memory allocation pool for payloads.
This DMA memory buffer with PcdDmaBufferSize is located at address
aligned at PcdDmaBufferAlignment after Payload reserved memory. Memory
type EfiRuntimeServicesData is used to indicate DMA memory type.
Stage1B calculates the DMA memory location using fixed PCDs so that
platform can set up DMA protection as early as possible after memory is
ready. In Stage1B or Stage2 platform code should use platform VTd
information to setup PMR to protect all low memory except for the DMA
buffer range. DMA memory will be added into memory pool at the entry
point of the payload. Before transfering to OS, the DMA memory protection
can be disabled, and the DMA memory pool can be reclaimed for OS usage.
Currently only boot media device will utilize the DMA buffer range for
block access operations. So it should only be required by payloads. GFX,
when enabled, will also use DMA. It will be targeted to the system stolen
memory which is not protected by PMR.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
For non UEFI boot, it is required to put an SMBIOS entry in legacy F
segment at 16-byte aligned boundary so that OS can locate the SMBIOS
by searching the region. This patch added this logic to add SMBIOS
entry at fixed location 0xFFF60. ACPI table has the similar legacy
root pointer at fixed location 0xFFF80.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL PCI enumeration code will zero out all PCI command registers and
PCI bridge control registers. However, FSP might have programmed some
of the registers already, and some of the bits are expected to be
preserved through the PCI enumeration. This patch addressed this issue
by only clearing the bits that are required during the PCI enumeration.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
PciEnumeration() scans a single PCI root bridge currently.
The PCI_ENUM_POLICY_INFO structure will be generated at build time,
and this will allow PCI enumeration more flexible.
typedef struct {
UINT8 DowngradeIo32;// default:1
UINT8 DowngradeMem64; // default:1
UINT8 DowngradePMem64;// default:1
UINT8 Reserved;
UINT8 BusScanType; // default:0 (0: list, 1: range)
UINT8 NumOfBus; // the number of BusScanItems
UINT8 BusScanItems[0];
} PCI_ENUM_POLICY_INFO;
Signed-off-by: Aiden Park <aiden.park@intel.com>
FPDT size should be FIRMWARE_PERFORMANCE_TABLE. And updated
this logic to correct the size and adjust next ACPI table
starting address.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This will allow OsLoader payload to boot to 64-bit kernel entry point.
If CPU supports 64-bit mode and a kernel image has 64-bit entry point,
OsLoader will switch to 64-bit long mode and jump to the 64-bit entry
point. Otherwise, continue to boot to 32-bit entry point.
- Ported necessary code from EDK2 VitualMemory.c in MdeModulePkg
- Moved PagingLib from BootloaderCorePkg to BootloaderCommonPkg
- Removed unused FlushCacheLine
- TBD: 64-bit IDT
Next step is to support 64-bit Payload.
- 32-bit compatible mode
- 64-bit CryptoLib
- etc.
Signed-off-by: Aiden Park <aiden.park@intel.com>
In order to sync up with EDK201911 stable release, it is required
to add missing header files in the INF file. Otherwise, the build
will throw warnings. This patch added the missing headers in INF
files.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch enabled Visual Studio 2017 Community 2017 build support.
The following were done:
- Added new method to detect VS2017 installation path and version
- Droped VS2005, VS2008, VS2010 and VS2012 build support. Only
VS2013 and VS2015 are supported.
- Fixed build issue in FspApiLib due to new compiler optimizations
- Synced the build support for QEMU FSP patch
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
CSME driver is not a component rather it is a driver to
update CSME binary, so it is not required to update status
of the driver to FWST ACPI table.
As part of the above change, gCsmeFWUDriverImageFileGuid is
moved from PayloadPkg.dec to bootloadercommonpkg.dec
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch did some of the following clean up:
- Rename *_HOB to *_PARAM for Stage1A/Stage1B/Stage2.
This is to avoid confusion between real HOB and the parameter
data block passed through stages.
- Rename BistVal to CpuBist.
This is to make it more clear.
- Add BUF_INFO definition.
BUF_INFO will be used as a general structure.
- Remove CarBase/Top in Stage1B HOB
They are not used at all.
- Clean memory allocation in Stage1A
Restructured the buffer allocations for Stage1A global
data so that it is easier to read and maintain.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch moved some library APIs into BootloaderCommonLib, including
GetComponentInfo() and GetComponentHash().
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
HASH_STORE_TABLE is updated and HASH_STORE_DATA is added
to provide info with variable length sizes. Usage bits would
notify for multiple component/key using the same hash.
These data structure would optimize the hash store size
in storage.
PcdHashStoreSize would define the size of Hash store
to allocate in bios bootup.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
Component Hash is passed with TpmExtendHash if available.
Hash Store is getting optimized on storage and this would avoid
setting component hash in hash table. SetComponent Hash API is
removed in bootloaderlib.
Added HashAlg param to TpmExtendHash for future purposes
where TPM PCR bank would be selected based on HashAlg.
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
EnableAvx ASM is included as part ExtraLibs.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Signed-off-by: Subash Lakkimsetti <subashx.lakkimsetti@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current SBL does not check the FSP Notify API return status. As a
result, if reset is requested, it is ignored by SBL. This patch
added FSP reset request check for FspMemoryInit, FspSiliconInit and
FspNotifyPhase.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This provides basic insertion sort API for Linked List. As part of change,
this insertion sort is used for PCI BAR calculation by its alignment
and for shell commands list by its name.
Signed-off-by: Aiden Park <aiden.park@intel.com>
There are multiple instances of sorting use case in SBL. For example,
memory map sorting and CPU APIC ID sorting. This patch added a generic
quick sort library to provide common sort API. As part of the change,
the quick sort API will be used for memory map and CPU APIC ID sorting.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch sorts the CPU info entry according to their thread distances.
It is required to list CPU thread with furthest distance first in MADT
so as to better utilize CPU resources.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL depends on flash map to locate all component info. It is
mandatory to keep flash map. HAVE_FLASH_MAP config option should
be removed. This patch removed this config option and the related
PcdFlashMapEnabled PCD.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
If FPDT->Length is just the size of FIRMWARE_PERFORMANCE_TABLE,
BOOT_PERFORMANCE_TABLE and S3_PERFORMANCE_TABLE are overwritten
by the next Table in ACPI init. Therefore, make the size in the
header as sizeof(INTERNAL_FIRMWARE_PERFORMANCE_TABLE) so that
the next table starts after INTERNAL_FIRMWARE_PERFORMANCE_TABLE.
Otherwise, S3 Perf Table can't be located on S3 resume path.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Error: conversion from 'UINT32' to 'UINT8', possible loss of data
MADT ProcessorId and ApicId has the size of UINT8. Cast the size from UINT32 to UINT8.
Change-Id: I3f46b2015b0d21c2b3e2f9389ecb8d5364ed5a5e
Signed-off-by: Aiden Park <aiden.park@intel.com>
Currently, the common hook UpdateMadt() was updating fixed size of
ProcessorLocalApic entries.
This allows the hook to append ProcessorLocalApic entries with the number
of detected CPUs in runtime.
Signed-off-by: Aiden Park <aiden.park@intel.com>
To make PlatformUpdateAcpiTable() hook its contents and length easily,
allocate a memory from low to high and appends each tables to higher direction
Signed-off-by: Aiden Park <aiden.park@intel.com>
By design, BootloaderCommonPkg should not refer to
BootloaderCorePkg. Hence removed those references in
the .inf files in Common pkg.
Moving SmbiosInitLib to Core pkg as it is a core feature.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Since HASH_INDEX_* is a 1:1 mapping with
COMP_TYPE_* we can remove HASH_INDEX_* and
replace with COMP_TYPE_*.
Also fix some misspellings.
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch added a ContainerLib to support load and location a
component from a specified container. It copies the component
from flash to memory, authenticate it, and then decompress it if
required. It can also be used to support load component from flash
map in SBL stage2 or payload, such as payload or e-payload.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
There are cases where temporary memory is required in stages. Since
MemoryAllocationLib instance for stages has no de-allocation function,
it needs special handling. This patch added temporary memory management
into standard MemoryAllocatoinLib interface.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SmmBase Info should not be expected by MpInit if the
platform/payload has not updated the Tseg region.
Check for the COMM signature before proceeding to Rebase.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Restore the register information saved during the
normal boot, on S3 resume path for UEFI payload only.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Synced up MdePkg, IntelFsp2Pkg and BaseTools to EDK2 stable tag
edk2-stable201905.
There are several changes for MdePkg and BaseTools.
MdePkg:
- Support light print to reduce SBL size
MdePkg\Library\BasePrintLib\PrintLibInternal.c
MdePkg\Include\Library\DebugLib.h
- TCG TPM2 spec changes and remove dependencies
MdePkg\Include\IndustryStandard\UefiTcgPlatform.h
MdePkg\Include\IndustryStandard\Tpm2Acpi.h
- Use old NVM protocol file
MdePkg\Include\Protocol\NvmExpressPassthru.h
- Removed unused files
BaseTools:
- Added LZ4 support
- Removed unused files
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch will add support for updating multiple firmwares
using a single capsule image.
Following modifications are made for existing firmware update flow
1) Gather and validate capsule image
2) State Machine will be set to capsule processing state.
3) Signature of the capsule image is now stored in reserved region
During each reboot until the end of firmware update, stored signature
will be compared against the capsule image signature to make sure
capsule image is not modified until the end of firmware update.
4) Process Capsule image to gather firmware images
5) Each Firmware image information will be stored in reserved region
using FW_UPDATE_COMP_STATUS. Update pending will be marked to
update pending state indicating that this image is not processed.
6) Firmware update will use the reserved region comp structures starting
with the first image with update pending state, update the comp update
pending field to processing and applies the image. After the update, pending
field will be updated to Done and updates the status of the update in the
component structure and moves on to next image found.
7) After all the component structure in the reserved region updating pending
field are set to Done. Firmware update mode is exited.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
Some platform might need do some platform specific init
on all the threads. So add a MP hook using a PCD.
Np impact for the platform that doesn't need this hook.
This patch also enable InSMM bit for APL.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Copying the MdePkg BaseMemoryLibSse2 library into
SBL for faster CopyMem and other routines to improve
boot performance every where except for Stage1A &
Stage1B due to 'movntdq' usage limitation in earlier
stages. Remove all of the X64 files since SBL is compiled
as 32-bit. Also patch PCI enumeration code to perform
manual memory copying (using SSE2 CopyMem gives some
issue as tested on APL).
The BaseMemoryLibSse2 folder was copied from EDK2
GitHub based on the following commit ID:
9344f0921518309295da89c221d10cbead8531aa
Signed-off-by: James Gutbub <james.gutbub@intel.com>
This patch added support for FWST ACPI table. This table
contains generic address structure which has pointer to the
EFI System Resource Table.
ESRT table for now supports only system firmware. This table
will provide the operating system and tools knowledge of what
is the last attempt status and version of the system firmare
update.
Signed-off-by: Raghava Gudla <raghava.gudla@intel.com>
This patch enabled DISABLE_NEW_DEPRECATED_INTERFACES build option by
default so that the deprecated APIs cannot be used in SBL source tree.
It is to enhance the coding for security.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Smm bases for all the procs need to be relocated on the
S3 resume path (as payload is not run) for Windows boot.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This patch adds FPDT table into ACPI table, and updates all
the performance data for S3 path.
It also update basic boot performance data for reset end.
Other boot performance data could be updated by UEFI payload.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current code refers hash store as "key store". It is confusing
since there is no key stored in the image at all. Instead, the
public key hash is stored. The patch renames the KeyStore
to HashStore.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
BootloaderCoreLib use same File_GUID and Base_NAME
with BootloaderLib, this patch updates INF to fix
this issue.
Signed-off-by: Guo Dong <guo.dong@intel.com>
Current MpFuncs.nasm used hard coded opcodes to support 16bit ASM.
It makes it difficult to maintain. Per suggestion, this patch
convered the 16bit opcodes into instruction directly.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
SBL has no intention to support SMI. However, on many hardware
platforms, there is no reliable way to prevent SMI from generating
through SMI IPI. In case it occurs, CPU will jump to the default
0x38000 location for execution, which exposes huge security issues.
The recommended solution is to do basic SMM base relocation and put
a dummy SMI handler (RSM) there for platform does not support SMI
disabling. In this way, the SMI will be ignored, and it also closes
the security concerns. This patch implemented basic SMM relocation.
It is under the control of a new PCD PcdSmmRebaseEnabled. By default,
it is disabled. To enable it, please set ENABLE_SMM_REBASE in
BoardConfig.py. As part of it, platform library needs to set
PcdSmramTsegBase and PcdSmramTsegSize properly in PreSiliconInit board
hook. Please take APL platform for reference.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
* Enable DebugAgentLib to support source level debug over serial
By default, source level debug is NOT enabled. ENABLE_SOURCE_DEBUG
needs to be set to 1 in BoardConfig.py of each Platforms.
- self.ENABLE_SOURCE_DEBUG = 1
As an initial drop, there are some limitations on APL platform.
- Stage1A does not include DebugAgentLib due to Stage1A size
limitation(32KB). Further optimization is required.
- DebugAgentLib supports ONLY POSTMEM debugging on APL currently.
Refer to EDKII Debugging:
- https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Debugging
- https://github.com/tianocore/tianocore.github.io/wiki/SourceLevelDebugPkg
Change-Id: Ia28c5470bc5755768f2b380cc1dabbcb8ee60f0d
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Additional changes for DebugAgent
- Adjust stage size depending on ENABLE_SOURCE_DEBUG Pcd value
- Add PeCoffFindAndReportImageInfo
- Fix debugger hang at Shell
Change-Id: I11b41e5ad610fcb2999e9d43e5dd8f8899e8265a
Signed-off-by: Aiden Park <aiden.park@intel.com>
* Move PeCoffFindAndReportImageInfo() from LitePeCoffLib to DebugAgentLib
Change-Id: I2c4ab4f9561dfd0536da1820048f0e5f2660e2ab
Signed-off-by: Aiden Park <aiden.park@intel.com>
Aiden Park