On TGL platform, when enable SR_IOV for PCI enumeration, system
hung due to insufficient PCI resource. GFX VF needs lots of MMIO
resource and it cannot be satisfied by SBL in 32 bit mode.
To address this issue, this patch extends the bus 0 downgrade
policy to further allow downgrading PCI bus 0 devices except for
GFX. Now the DowngradeBus0 policy has following values:
0: Do not downgrade PCI devices on bus 0
1: Downgrade all PCI devices on bus 0
2: Downgrade all PCI devices on bus 0 but GFX
3: Reserved
By default, it has the same behavior as before. If platform needs
to download bus 0 devices but GFX, the new value 2 can be used.
This has been tested on TGL, and it worked as expected.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Current PciBus lib expects the root bridge resource base should not be
greater than limit. It is true for normal case. However, to mark the
source is unavailable, the base could be less than the limit in some
case. PCI bus lib should only validate the resource that does have a
request.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adds a platform hook function ability
in Pci Enum Lib to enable platform to perform
PCI Enum specific work-around routines.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
- fix __aullshr link error due to compiler intrinsics functions
for NOOPT build in Windows
- adjust Stage1A/TopSwap/OsLoader FD size for NOOPT target
- adjust Stage2 size for NOOPT target when DEBUG FSP is used
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
This will disable all PCI bus master by default, and enable it only if
- the original bus master was enabled before PCI enumeration
- Or the device is PCI Bridge
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current PCI Enum Lib scopes for only Apperture resources
for a PPB. But some OSes (like ESXi) expect BAR0 & BAR1
(Offset 0x10/0x14) to be allocated resources accordingly.
Otherwise, PPB enumeration doesnt happen correctly and
devices behind PPB are not registered at all.
This patch adds the functionality to assign valid resources
to BAR0(0x10) and BAR1(0x14) for a PPB also.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This introduces an additional PCI Enumeration option.
- self._PCI_ENUM_FLAG_ALLOC_PMEM_FIRST
By deafult, the option will allocate PCI resource by ascending order
(MEM32->PMEM32->MEM64->PMEM64). If it's set to 1, by reversed order.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Current PCI resource PCD bases are defined as fixed type. It
makes it impossible to dynamically adjust the base at runtime.
This patch changed it to be module patchable so that platform
can update when required.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
ProgramBar() routine uses 'OrgBarType' field to
determine BarType. So, if a BarType is valid, copy
it to OrgBarType for VF also.
Signed-off-by: Talamudupula <stalamudupula@gmail.com>
This introduces a new PCD 'PcdPciResAllocTableBase' to allow a platform
to provide its specific PCI resource allocation pool at runtime.
PCI Enumerator will allocate required resources in the range.
If the PCD is not provided, a default range will be used.
Signed-off-by: Aiden Park <aiden.park@intel.com>
In 64-bit operation, some PCI devices have high mmio BARs,
but 32-bit FSP can only access 32-bit memory space.
This introduces and additional PCI resource downgrade option
to downgrade all PCI devices under Bus-0.
- self._PCI_ENUM_DOWNGRADE_BUS0 = 1
Force to have 32-bit BAR for all Bus-0 devices
Signed-off-by: Aiden Park <aiden.park@intel.com>
All child devices under a PPB must be in scope of its PPB's decode space.
Therefore, all PPB checks the decode capability and downgrades its child
devices' resources accordingly.
Signed-off-by: Aiden Park <aiden.park@intel.com>
The following commit 9fcb3a6be1
caused a regression on PCI bridge resource allocation. At minimum
the PCI bridge needs to have IO apperture aligned at 4KB and MMIO
apperture aligned at 1MB. The new code did not adjust the
alignment for P2P bridge following this rule. This patch fixed
this issue.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
This patch adjusted some alignment on PCI resource allocation so
that PCI resource is more efficently utilized. It aslo adjusted
the framebuffer MTRR range to match PCI resource allocation.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
When multiple level of PCI bridges exists on a platform, current
SBL PCI bus library could not find all devices. This issue was
caused by incorrect root bridge bus limit got from the data
structure. This patch fixed this issue.
It also fixed#800.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
A PPB PCI_IO_DEVICE instance has BIT31 in its Address field to identify
the device as PPB type. But, the bit is set after scanning the PPB.
This skips PPB type check in PciGetMaxBusNumber() and let a caller
guarantee PPB type check instead of adding a field in PCI_IO_DEVICE
for PPB device.
Signed-off-by: Aiden Park <aiden.park@intel.com>
At PciScanBus, a PCI bridge sets PCI Bridge Subordinate Bus to 0xFF
temporary to go thru any PPB. But, a platform has some reserved buses
(ex. 0xFB-0xFF) on PCI hierarchy, and writing 0xFF regardless of
reserved bus ranges causes system hang.
Therefore, PciGetMaxBusNumber will be used for PCI Bridge Subordinate
Bus and it gets the number of buses from PCI Enum Policy to skip the
reserved buses.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will support PCI SR-IOV(Single Root I/O Virtualization).
- Controlled by PcdSrIovSupport (SUPPORT_SR_IOV in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will enable ARI(Alternative Routing-ID Interpretation).
- Controlled by PcdAriSupport (SUPPORT_ARI in BoardConfig)
- Disabled by default
Signed-off-by: Aiden Park <aiden.park@intel.com>
Correct the index reported while dumping the
PCI resource information.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Co-authored-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Fix unresolved external and type-cast issues for X64 build.
Signed-off-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
Co-authored-by: Sai Talamudupula <sai.kiran.talamudupula@intel.com>
This will create a HOB for PCI Root Bridge Resource information.
The PciRootBridgeInfo Hob can be used to update resource ranges of multiple
root bridges in platform PCI tree ASL.
A payload can also use this info to skip duplicated root bridge scan.
Signed-off-by: Aiden Park <aiden.park@intel.com>
This patch allows both 32/64-bit addressing properly.
- Pointer type cast with UINTN
- Add missing EFIAPI for APIs
Signed-off-by: Aiden Park <aiden.park@intel.com>
SBL PCI enumeration code will zero out all PCI command registers and
PCI bridge control registers. However, FSP might have programmed some
of the registers already, and some of the bits are expected to be
preserved through the PCI enumeration. This patch addressed this issue
by only clearing the bits that are required during the PCI enumeration.
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
PciEnumeration() scans a single PCI root bridge currently.
The PCI_ENUM_POLICY_INFO structure will be generated at build time,
and this will allow PCI enumeration more flexible.
typedef struct {
UINT8 DowngradeIo32;// default:1
UINT8 DowngradeMem64; // default:1
UINT8 DowngradePMem64;// default:1
UINT8 Reserved;
UINT8 BusScanType; // default:0 (0: list, 1: range)
UINT8 NumOfBus; // the number of BusScanItems
UINT8 BusScanItems[0];
} PCI_ENUM_POLICY_INFO;
Signed-off-by: Aiden Park <aiden.park@intel.com>
This will fully support PatchCheck.py.
- Remove all trailing whitespace
- Convert LF to CRLF by default
- Update EFI_D_* to DEBUG_*
- Re-enable CRLF check in PatchCheck.py
Signed-off-by: Aiden Park <aiden.park@intel.com>
This provides basic insertion sort API for Linked List. As part of change,
this insertion sort is used for PCI BAR calculation by its alignment
and for shell commands list by its name.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Synced up MdePkg, IntelFsp2Pkg and BaseTools to EDK2 stable tag
edk2-stable201905.
There are several changes for MdePkg and BaseTools.
MdePkg:
- Support light print to reduce SBL size
MdePkg\Library\BasePrintLib\PrintLibInternal.c
MdePkg\Include\Library\DebugLib.h
- TCG TPM2 spec changes and remove dependencies
MdePkg\Include\IndustryStandard\UefiTcgPlatform.h
MdePkg\Include\IndustryStandard\Tpm2Acpi.h
- Use old NVM protocol file
MdePkg\Include\Protocol\NvmExpressPassthru.h
- Removed unused files
BaseTools:
- Added LZ4 support
- Removed unused files
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Copying the MdePkg BaseMemoryLibSse2 library into
SBL for faster CopyMem and other routines to improve
boot performance every where except for Stage1A &
Stage1B due to 'movntdq' usage limitation in earlier
stages. Remove all of the X64 files since SBL is compiled
as 32-bit. Also patch PCI enumeration code to perform
manual memory copying (using SSE2 CopyMem gives some
issue as tested on APL).
The BaseMemoryLibSse2 folder was copied from EDK2
GitHub based on the following commit ID:
9344f0921518309295da89c221d10cbead8531aa
Signed-off-by: James Gutbub <james.gutbub@intel.com>
Maurice Ma