FSP version is 0C00DE40
platform version is 1.4
Microcode Files are: ['m_07_90672_00000036.pdb', 'm_32_b0671_00000123.pdb']
Signed-off-by: Randy <randy.lin@intel.com>
- FSP version is NEX RPL-P MR2 (0C.01.DE.40)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.2
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
- FSP version is IoT RPL-P MR1 (0C.01.CC.20)
- Microcode version is 411d
- VBT version is 253
- platform version is 1.1
- minor fixes for BoardConfigRplp.py and StitchIfwi.py
- allow TCC/TSN to be enabled by FuSa DLT file
Signed-off-by: Vincent Chen <vincent.chen@intel.com>
* feat: [RPL-P] Upstream RPL-P code.
Upstream internal RPL-P code to Sbl open source.
FspsUpdUpdateLib updated for compatibility with both RPL-P and RPL-S.
RPL-P specific TCC code will be removed with TCC binary removal after
baseline is upstreamed.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* fix: [RPL-P] Addressing code cleanup review comments.
Function header comments and parameters cleaned up in FusaConfigLib.
FSP commit updated to latest, vbt removed in favor of local file.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPL-P] Removed TCC Subregion support.
Current TCC feature design removes use of TCC subregions.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
* [RPL-P] Moved ucode and FSP to Silicon dir, removed PLT_SOURCE, added VBTs
FSP and microcode moved to Silicon folder to be in line with other
platforms. Removed references to PLT_SOURCE env variable. Added VBTs
and removed them from .gitignore.
Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
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Signed-off-by: Bejean Mosher <bejean.mosher@intel.com>
Randy