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fix: [MTL] Can't output log to EC port. 

Verified on MTL-P platform with set self.DEBUG_PORT_NUMBER = 0xFF

Signed-off-by: Randy <randy.lin@intel.com>
This commit is contained in:
Randy 2024-04-29 15:01:45 +08:00 committed by Guo Dong
parent 6bd0042de1
commit f8f6ac4bce
3 changed files with 32 additions and 21 deletions
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6
Silicon/MeteorlakePkg/Include/Register/PchRegsLpc.h
View File

@ -26,9 +26,10 @@
#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
#define B_LPC_CFG_GENX_DEC_EN 0x00000001
#define B_LPC_CFG_GENX_DEC_EN 0x00000001
#define B_LPC_CFG_IOE_SE BIT12
#define R_LPC_CFG_BDE 0xD8 ///< BIOS decode enable
#define R_IOC_CFG_LPCIOD 0x7A70 ///< LPC I/O Decode Ranges
#define R_IOC_CFG_LPCIOE 0x7A74 ///< LPC I/O Enables
//
// APM Registers
@ -37,7 +38,6 @@
#define R_PCH_IO_APM_STS 0xB3
#define R_LPC_CFG_BC 0xDC ///< Bios Control
//
//
// eSPI Responder registers

2
Silicon/MeteorlakePkg/Include/Register/SaRegsHostBridge.h
View File

@ -648,4 +648,6 @@ This bit is either part of the PCI Express Base Address (R/W) or part of the Add
/// Description of GMADRBAR bit (38:27)
/// Description of VTDBAR bit (38:12)
///
#define MCHBAR_HOSTBRIDGE_CFG_REG 0x48
#endif

45
Silicon/MeteorlakePkg/Library/PlatformHookLib/PlatformHookLib.c
View File

@ -1,7 +1,7 @@
/** @file
The platform hook library.
Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020 - 2024, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -19,6 +19,8 @@
#include <IndustryStandard/Pci.h>
#include <Register/SerialIoUartRegs.h>
#include <Include/PcrDefine.h>
#include <Register/SaRegsHostBridge.h>
#include <Register/PchRegsLpc.h>
#define MM_PCI_OFFSET(Bus, Device, Function) \
( (UINTN)(Bus << 20) + \
@ -106,26 +108,33 @@ LegacySerialPortInitialize (
VOID
)
{
UINTN eSPIBaseAddr;
UINT16 Data16;
UINTN EspiBaseAddr;
UINT16 IoDecodeRanges;
UINT16 IoDecodeEnable;
UINT32 MchBar;
eSPIBaseAddr = PCI_LIB_ADDRESS (
DEFAULT_PCI_BUS_NUMBER_PCH,
PCI_DEVICE_NUMBER_PCH_ESPI,
PCI_FUNCTION_NUMBER_PCH_ESPI,
0);
// Decode range value, Bit 6:4: ComB range, Bit 2:0: ComA range
EspiBaseAddr = PCI_LIB_ADDRESS (DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_ESPI, PCI_FUNCTION_NUMBER_PCH_ESPI, 0);
IoDecodeRanges = PciRead16 (EspiBaseAddr + R_LPC_CFG_IOD) & 0xFF84;
IoDecodeRanges |= (V_LPC_CFG_IOD_COMB_2F8 << N_LPC_CFG_IOD_COMB);
IoDecodeRanges |= (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA);
Data16 = PciRead16 (eSPIBaseAddr + R_LPC_CFG_IOD);
Data16 |= (V_LPC_CFG_IOD_COMB_2F8 << N_LPC_CFG_IOD_COMB);
Data16 |= (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA);
MmioWrite16 (PCH_PCR_ADDRESS (PID_DMI, R_PCH_DMI_PCR_LPCIOD), Data16);
PciWrite16 (eSPIBaseAddr + R_LPC_CFG_IOD, Data16);
// Set PCH LPC/eSPI IO decode ranges in IOC
MchBar = PciRead32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, MCHBAR_HOSTBRIDGE_CFG_REG));
MchBar &= 0xFFFE0000;
MmioWrite32 (MchBar + R_IOC_CFG_LPCIOD, IoDecodeRanges);
Data16 = PciRead16 (eSPIBaseAddr + R_LPC_CFG_IOE);
Data16 |= B_LPC_CFG_IOE_CBE;
Data16 |= B_LPC_CFG_IOE_CAE;
MmioWrite16 (PCH_PCR_ADDRESS (PID_DMI, R_PCH_DMI_PCR_LPCIOE), Data16);
PciWrite16 (eSPIBaseAddr + R_LPC_CFG_IOE, Data16);
// Program same decode value in LPC/eSPI PCI
PciWrite16 (EspiBaseAddr + R_LPC_CFG_IOD, IoDecodeRanges);
IoDecodeEnable = PciRead16 (EspiBaseAddr + R_LPC_CFG_IOE);
IoDecodeEnable |= B_LPC_CFG_IOE_SE;
IoDecodeEnable |= B_LPC_CFG_IOE_CBE;
IoDecodeEnable |= B_LPC_CFG_IOE_CAE;
IoDecodeEnable |= B_LPC_CFG_IOE_ME1;
MmioWrite32 (MchBar + R_IOC_CFG_LPCIOE, IoDecodeEnable);
PciWrite16 (EspiBaseAddr + R_LPC_CFG_IOE, IoDecodeEnable);
return RETURN_SUCCESS;
}