fix: [MTL] Can't output log to EC port.
Verified on MTL-P platform with set self.DEBUG_PORT_NUMBER = 0xFF Signed-off-by: Randy <randy.lin@intel.com>
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@ -26,9 +26,10 @@
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#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
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#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
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#define B_LPC_CFG_GENX_DEC_EN 0x00000001
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#define B_LPC_CFG_GENX_DEC_EN 0x00000001
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#define B_LPC_CFG_GENX_DEC_EN 0x00000001
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#define B_LPC_CFG_GENX_DEC_EN 0x00000001
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#define B_LPC_CFG_IOE_SE BIT12
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#define R_LPC_CFG_BDE 0xD8 ///< BIOS decode enable
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#define R_IOC_CFG_LPCIOD 0x7A70 ///< LPC I/O Decode Ranges
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#define R_IOC_CFG_LPCIOE 0x7A74 ///< LPC I/O Enables
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//
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//
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// APM Registers
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// APM Registers
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@ -37,7 +38,6 @@
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#define R_PCH_IO_APM_STS 0xB3
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#define R_PCH_IO_APM_STS 0xB3
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#define R_LPC_CFG_BC 0xDC ///< Bios Control
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#define R_LPC_CFG_BC 0xDC ///< Bios Control
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//
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//
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//
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//
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// eSPI Responder registers
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// eSPI Responder registers
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@ -648,4 +648,6 @@ This bit is either part of the PCI Express Base Address (R/W) or part of the Add
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/// Description of GMADRBAR bit (38:27)
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/// Description of GMADRBAR bit (38:27)
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/// Description of VTDBAR bit (38:12)
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/// Description of VTDBAR bit (38:12)
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///
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///
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#define MCHBAR_HOSTBRIDGE_CFG_REG 0x48
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#endif
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#endif
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@ -1,7 +1,7 @@
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/** @file
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/** @file
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The platform hook library.
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The platform hook library.
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Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2020 - 2024, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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**/
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@ -19,6 +19,8 @@
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#include <IndustryStandard/Pci.h>
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#include <IndustryStandard/Pci.h>
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#include <Register/SerialIoUartRegs.h>
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#include <Register/SerialIoUartRegs.h>
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#include <Include/PcrDefine.h>
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#include <Include/PcrDefine.h>
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#include <Register/SaRegsHostBridge.h>
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#include <Register/PchRegsLpc.h>
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#define MM_PCI_OFFSET(Bus, Device, Function) \
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#define MM_PCI_OFFSET(Bus, Device, Function) \
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( (UINTN)(Bus << 20) + \
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( (UINTN)(Bus << 20) + \
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@ -106,26 +108,33 @@ LegacySerialPortInitialize (
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VOID
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VOID
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)
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)
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{
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{
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UINTN eSPIBaseAddr;
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UINTN EspiBaseAddr;
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UINT16 Data16;
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UINT16 IoDecodeRanges;
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UINT16 IoDecodeEnable;
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UINT32 MchBar;
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eSPIBaseAddr = PCI_LIB_ADDRESS (
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// Decode range value, Bit 6:4: ComB range, Bit 2:0: ComA range
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DEFAULT_PCI_BUS_NUMBER_PCH,
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EspiBaseAddr = PCI_LIB_ADDRESS (DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_ESPI, PCI_FUNCTION_NUMBER_PCH_ESPI, 0);
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PCI_DEVICE_NUMBER_PCH_ESPI,
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IoDecodeRanges = PciRead16 (EspiBaseAddr + R_LPC_CFG_IOD) & 0xFF84;
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PCI_FUNCTION_NUMBER_PCH_ESPI,
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IoDecodeRanges |= (V_LPC_CFG_IOD_COMB_2F8 << N_LPC_CFG_IOD_COMB);
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0);
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IoDecodeRanges |= (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA);
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Data16 = PciRead16 (eSPIBaseAddr + R_LPC_CFG_IOD);
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// Set PCH LPC/eSPI IO decode ranges in IOC
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Data16 |= (V_LPC_CFG_IOD_COMB_2F8 << N_LPC_CFG_IOD_COMB);
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MchBar = PciRead32 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, MCHBAR_HOSTBRIDGE_CFG_REG));
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Data16 |= (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA);
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MchBar &= 0xFFFE0000;
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MmioWrite16 (PCH_PCR_ADDRESS (PID_DMI, R_PCH_DMI_PCR_LPCIOD), Data16);
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MmioWrite32 (MchBar + R_IOC_CFG_LPCIOD, IoDecodeRanges);
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PciWrite16 (eSPIBaseAddr + R_LPC_CFG_IOD, Data16);
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Data16 = PciRead16 (eSPIBaseAddr + R_LPC_CFG_IOE);
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// Program same decode value in LPC/eSPI PCI
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Data16 |= B_LPC_CFG_IOE_CBE;
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PciWrite16 (EspiBaseAddr + R_LPC_CFG_IOD, IoDecodeRanges);
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Data16 |= B_LPC_CFG_IOE_CAE;
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MmioWrite16 (PCH_PCR_ADDRESS (PID_DMI, R_PCH_DMI_PCR_LPCIOE), Data16);
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IoDecodeEnable = PciRead16 (EspiBaseAddr + R_LPC_CFG_IOE);
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PciWrite16 (eSPIBaseAddr + R_LPC_CFG_IOE, Data16);
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IoDecodeEnable |= B_LPC_CFG_IOE_SE;
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IoDecodeEnable |= B_LPC_CFG_IOE_CBE;
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IoDecodeEnable |= B_LPC_CFG_IOE_CAE;
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IoDecodeEnable |= B_LPC_CFG_IOE_ME1;
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MmioWrite32 (MchBar + R_IOC_CFG_LPCIOE, IoDecodeEnable);
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PciWrite16 (EspiBaseAddr + R_LPC_CFG_IOE, IoDecodeEnable);
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return RETURN_SUCCESS;
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return RETURN_SUCCESS;
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}
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}
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