diff --git a/Platform/TigerlakeBoardPkg/BoardConfig.py b/Platform/TigerlakeBoardPkg/BoardConfig.py
index 312b63da..db84acf5 100644
--- a/Platform/TigerlakeBoardPkg/BoardConfig.py
+++ b/Platform/TigerlakeBoardPkg/BoardConfig.py
@@ -25,7 +25,7 @@ class Board(BaseBoard):
 
         self.VERINFO_IMAGE_ID       = 'SBL_TGL'
         self.VERINFO_PROJ_MAJOR_VER = 1
-        self.VERINFO_PROJ_MINOR_VER = 7
+        self.VERINFO_PROJ_MINOR_VER = 8
         self.VERINFO_SVN            = 1
         self.VERINFO_BUILD_DATE     = time.strftime("%m/%d/%Y")
 
diff --git a/Silicon/TigerlakePkg/FspBin/FspBin.inf b/Silicon/TigerlakePkg/FspBin/FspBin.inf
index 8c52a260..4908e5fb 100644
--- a/Silicon/TigerlakePkg/FspBin/FspBin.inf
+++ b/Silicon/TigerlakePkg/FspBin/FspBin.inf
@@ -11,7 +11,7 @@
 
 [UserExtensions.SBL."CloneRepo"]
   REPO    = https://github.com/intel/FSP.git
-  COMMIT  = 9ff157011c695a99488576b2ae98d58609579179
+  COMMIT  = cfdf71ddce304e411e46d88f5ef635c6a515a54d
 
 [UserExtensions.SBL."CopyList"]
   TigerLakeFspBinPkg/TGL_IOT/Fsp.fd                    : Silicon/TigerlakePkg/FspBin/FspDbg.bin