From c76e3272d4ff63f34c769f7a10e28bddca9d847f Mon Sep 17 00:00:00 2001 From: Maurice Ma Date: Thu, 18 Feb 2021 20:32:28 -0800 Subject: [PATCH] Fix MTRR mask programming for GFX framebuffer Linux reported incorrect MTRR mask programming in SBL. This patch fixed this issue by using the proper MTRR mask for GFX FB. Signed-off-by: Maurice Ma --- .../Stage2BoardInitLib/Stage2BoardInitLib.c | 6 +- .../Stage2BoardInitLib/Stage2BoardInitLib.h | 1 + Silicon/ApollolakePkg/Include/CpuRegs.h | 64 ------------------- .../Library/SocInfoLib/SocInfoLib.c | 3 +- .../Library/SocInfoLib/SocInfoLib.inf | 1 + 5 files changed, 9 insertions(+), 66 deletions(-) diff --git a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c index 80dd440a..a600ee91 100644 --- a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c +++ b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.c @@ -697,6 +697,8 @@ SetFrameBufferWriteCombining ( UINT32 Data; UINT32 GfxPciBase; UINT64 Base64; + UINT64 Mask64; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; // Skip if GFX device does not exist GfxPciBase = PCI_LIB_ADDRESS (0, 2, 0, 0); @@ -724,7 +726,9 @@ SetFrameBufferWriteCombining ( // The 1st 256MB from PcdPciResourceMem32Base will be consumed by MEM32 resource. // And framebuffer should be allocated to the next 256MB aligned address. AsmWriteMsr64 (MsrIdx, Base64 | CACHE_WRITECOMBINING); - AsmWriteMsr64 (MsrIdx + 1, 0xF00000000ULL + B_EFI_MSR_CACHE_MTRR_VALID + (UINT32)(~(SIZE_256MB - 1))); + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL); + Mask64 = (LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1) & 0xFFFFFFFF00000000ULL; + AsmWriteMsr64 (MsrIdx + 1, Mask64 + B_EFI_MSR_CACHE_MTRR_VALID + (UINT32)(~(SIZE_256MB - 1))); } else { DEBUG ((DEBUG_WARN, "Failed to find a free MTRR pair for framebuffer!\n")); } diff --git a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.h b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.h index 926d780f..3c4e64d5 100644 --- a/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.h +++ b/Platform/ApollolakeBoardPkg/Library/Stage2BoardInitLib/Stage2BoardInitLib.h @@ -69,6 +69,7 @@ #include #include #include +#include #include #define IOC_UART_PPR_CLK_N_DIV 0x64 diff --git a/Silicon/ApollolakePkg/Include/CpuRegs.h b/Silicon/ApollolakePkg/Include/CpuRegs.h index 988f7b58..34b9a788 100644 --- a/Silicon/ApollolakePkg/Include/CpuRegs.h +++ b/Silicon/ApollolakePkg/Include/CpuRegs.h @@ -82,70 +82,6 @@ #define CACHE_WRITEPROTECTED 5 #define CACHE_WRITEBACK 6 -#define CPUID_SIGNATURE 0x0 -#define CPUID_VERSION_INFO 0x1 -#define CPUID_FUNCTION_4 0x4 -#define CPU_CACHE_TYPE_MASK 0x1F -#define CPU_CACHE_LEVEL_MASK 0x07 -#define CPU_CACHE_ASSOCIATIVITY_MASK 0x03FF -#define CPU_CACHE_PARTITION_MASK 0x03FF -#define CPU_CACHE_LINE_SIZE_MASK 0x0FFF -#define B_CPUID_VERSION_INFO_ECX_MWAIT BIT3 -#define B_CPUID_VERSION_INFO_ECX_VME BIT5 -#define B_CPUID_VERSION_INFO_ECX_SME BIT6 -#define B_CPUID_VERSION_INFO_ECX_EIST BIT7 -#define B_CPUID_VERSION_INFO_ECX_TM2 BIT8 -#define B_CPUID_VERSION_INFO_ECX_DCA BIT18 -#define B_CPUID_VERSION_INFO_ECX_AES BIT25 -#define B_CPUID_VERSION_INFO_ECX_X2APIC BIT21 -#define B_CPUID_VERSION_INFO_EDX_XD BIT20 -#define B_CPUID_VERSION_INFO_EDX_HT BIT28 -#define B_CPUID_VERSION_INFO_EDX_TM1 BIT29 - -#define CPUID_CACHE_INFO 0x2 -#define CPUID_SERIAL_NUMBER 0x3 -#define CPUID_CACHE_PARAMS 0x4 - -// -// CPU ID Instruction defines -// -#define V_CPUID_CACHE_TYPE_MASK 0x1F -#define B_CPUID_CACHE_TYPE_DATA 0x1 -#define B_CPUID_CACHE_TYPE_INSTRUCTION 0x2 -#define B_CPUID_CACHE_TYPE_UNIFIED 0x3 -#define V_CPUID_CACHE_LEVEL_MASK 0xE0 -#define B_CPUID_CACHE_LEVEL_SHIFT 5 -#define B_CPUID_CACHE_PARAMS_WAYS_SHIFT 22 -#define B_CPUID_CACHE_PARAMS_PARTITIONS_SHIFT 12 -#define CPUID_MONITOR_MWAIT_PARAMS 0x5 -#define B_CPUID_MONITOR_MWAIT_ECX_EXTENSIONS BIT0 -#define B_CPUID_MONITOR_MWAIT_EDX_CSTATE BIT0 -#define V_CPUID_MONITOR_MWAIT_EDX_ENHANCED_CSTATE 0x2 -#define CPUID_POWER_MANAGEMENT_PARAMS 0x6 -#define B_CPUID_POWER_MANAGEMENT_EAX_TURBO BIT1 -#define B_CPUID_POWER_MANAGEMENT_EAX_FINE_GRAINED_CLOCK_MODULATION BIT5 -#define B_CPUID_POWER_MANAGEMENT_ECX_ENERGY_EFFICIENT_POLICY_SUPPORT BIT3 -#define B_CPUID_POWER_MANAGEMENT_EAX_HWP BIT7 -#define B_CPUID_POWER_MANAGEMENT_EAX_HWP_LVT_INTERRUPT_SUPPORT BIT9 -#define B_CPUID_FUNCTION7_EBX_RTIT_SUPPORT BIT25 -#define B_CPUID_FUNCTION20_ECX_TOPA_SUPPORT BIT0 -#define B_CPUID_FUNCTION20_ECX_SINGLE_RANGE_SUPPORT BIT2 -#define CPUID_EDRAM_CAPABILITY 0x4 -#define CPUID_FUNCTION_7 0x7 -#define CPUID_FUNCTION_8 0x8 -#define CPUID_FUNCTION_20 0x14 -#define CPUID_DCA_PARAMS 0x9 -#define CPUID_FUNCTION_A 0xA -#define CPUID_CORE_TOPOLOGY 0xB - -#define CPUID_EXTENDED_FUNCTION 0x80000000 -#define CPUID_EXTENDED_CPU_SIG 0x80000001 -#define CPUID_BRAND_STRING1 0x80000002 -#define CPUID_BRAND_STRING2 0x80000003 -#define CPUID_BRAND_STRING3 0x80000004 -#define CPUID_L2_CACHE_FEATURE 0x80000006 -#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008 - // // MSR defines // diff --git a/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.c b/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.c index 35dd439d..6074ca93 100644 --- a/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.c +++ b/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.c @@ -12,6 +12,7 @@ #include #include #include +#include typedef struct { @@ -75,7 +76,7 @@ GetCpuNumCores ( ) { UINT32 Ebx; - AsmCpuidEx (CPUID_CORE_TOPOLOGY, 1, NULL, &Ebx, NULL, NULL); // BWG 3.1.8 + AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, NULL, &Ebx, NULL, NULL); // BWG 3.1.8 return (Ebx & 0xffff); } diff --git a/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.inf b/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.inf index 8ea7b1e6..b8edd807 100644 --- a/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.inf +++ b/Silicon/ApollolakePkg/Library/SocInfoLib/SocInfoLib.inf @@ -24,6 +24,7 @@ [Packages] MdePkg/MdePkg.dec + BootloaderCommonPkg/BootloaderCommonPkg.dec BootloaderCorePkg/BootloaderCorePkg.dec Silicon/ApollolakePkg/ApollolakePkg.dec